diff --git a/.gitlint_qemu b/.gitlint_qemu new file mode 100644 index 0000000000000000000000000000000000000000..c4e4cf7f036ec0c9883ea13d8febb47316a1d7f4 --- /dev/null +++ b/.gitlint_qemu @@ -0,0 +1,39 @@ +# increase the default remote timeout in gdb because +# Windows libusb transactions could be slow +set remotetimeout 100000 + +# gdb connect to openocd in port 3333 +target extended-remote localhost:1234 + +# start openocd working queue, monitor followed with openocd command here +# monitor init + +# force to use hardware breakpoint, otherwise use software breakpoint +# for e2000d/q, num of hardware breakpoints supposed to be 6 +# monitor gdb_breakpoint_override hardware + +# load elf image +# load ./build/zephyr/zephyr.elf + +# in case symbols skip load，load agin +file ./build/zephyr/zephyr.elf + +# we can break at the beginning of code by address or by symbol +#break _boot + +# add more breakpoints in application +#break JtagTouchRegisters +#break JtagTouchMemory +# break bubbleSort +# break JtagPostSort +#break bubbleSortCXX + +# show all breakspoints we before running +# info breakpoints + +# show [-0x10 ~ +0x10 ] range of instructions when breaked +# display /10i $pc-16 + +# start running +# continue +si diff --git a/arch/arm/core/Kconfig b/arch/arm/core/Kconfig index 41c2b1f76842a44cea214a0b4ccf91e800e9a30b..2b98e64f13d3d3b3e5661fb1bd472bcc9525be8e 100644 --- a/arch/arm/core/Kconfig +++ b/arch/arm/core/Kconfig @@ -70,6 +70,11 @@ config GDBSTUB_BUF_SZ # registers - 336 HEX letters default 350 if GDBSTUB +config CPU_AARCH32_ARMV8 + bool + help + This option signifies the use of a CPU of the Armv8 family. + config ISA_THUMB2 bool help diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 4095a277c613883a9668a36c49661c20818acea5..e5130af91e418e56d065d16a379226295cc33898 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -13,6 +13,43 @@ # CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not # exposed if one selects a different ARM Cortex Family (Cortex-M). +config CPU_PHYTIUM_FT310 + bool + select CPU_AARCH32_CORTEX_A + select CPU_AARCH32_ARMV8 + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select ARMV7_A + help + This option signifies the use of a FT310 CPU. + +if CPU_PHYTIUM_FT310 + config AARCH64_2_AARCH32 + bool + help + Example Convert aarch64 to aarch32 + +endif + +config CPU_PHYTIUM_FT663 + bool + select CPU_AARCH32_CORTEX_A + select CPU_AARCH32_ARMV8 + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select ARMV7_A + help + This option signifies the use of a FT663 CPU. + +if CPU_PHYTIUM_FT663 + config AARCH64_2_AARCH32 + bool + help + Example Convert aarch64 to aarch32 + +endif + + config CPU_CORTEX_A9 bool select CPU_AARCH32_CORTEX_A diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index 0b107fbf596afc7226f488bb2708ae6237981649..cc3da81ab7db52273b574eeb439d86c1cac1632b 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -34,6 +34,87 @@ GDATA(z_arm_undef_stack) GTEXT(z_arm_platform_init) #endif +SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) +#if defined(CONFIG_AARCH64_2_AARCH32) +aarch64_2_aarch32: + .long 0xd5384240 /* mrs x0, currentel */ + .long 0xd342fc00 /* lsr x0, x0, #2 */ + .long 0x92400400 /* and x0, x0, #0x3 */ + .long 0xf1000c1f /* cmp x0, #0x3 */ + .long 0x540003a1 /* b.ne 1d0080c4 */ + +el3_mode: + .long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ + .long 0xb2400000 /* orr x0, x0, #0x1 */ + .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + + .long 0xd2803620 /* mov x0, #0x1b1 */ + .long 0xd51e1100 /* msr scr_el3, x0 */ + .long 0xd2867fe0 /* mov x0, #0x33ff */ + .long 0xd51c1140 /* msr cptr_el2, x0 */ + .long 0xd2810000 /* mov x0, #0x800 */ + .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ + .long 0xd5181000 /* msr sctlr_el1, x0 */ + .long 0x910003e0 /* mov x0, sp */ + .long 0xd51c4100 /* msr sp_el1, x0 */ + .long 0xd53ec000 /* mrs x0, vbar_el3 */ + .long 0xd518c000 /* msr vbar_el1, x0 */ + .long 0xd2803a60 /* mov x0, #0x1d3 */ + .long 0xd51e4000 /* msr spsr_el3, x0 */ + .long 0x10000500 /* adr x0, 1d008158 */ + .long 0xd51e4020 /* msr elr_el3, x0 */ + .long 0xd69f03e0 /* eret */ + +el2_mode: + .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ + .long 0xb2400000 /* orr x0, x0, #0x1 */ + .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd53ce100 /* mrs x0, cnthctl_el2 */ + .long 0xb2400400 /* orr x0, x0, #0x3 */ + .long 0xd51ce100 /* msr cnthctl_el2, x0 */ + .long 0xd51ce07f /* msr cntvoff_el2, xzr */ + .long 0xd5380000 /* mrs x0, midr_el1 */ + .long 0xd53800a1 /* mrs x1, mpidr_el1 */ + .long 0xd51c0000 /* msr vpidr_el2, x0 */ + .long 0xd51c00a1 /* msr vmpidr_el2, x1 */ + .long 0xd2867fe0 /* mov x0, #0x33ff */ + .long 0xd51c1140 /* msr cptr_el2, x0 */ + .long 0xd51c117f /* msr hstr_el2, xzr */ + .long 0xd2a00600 /* mov x0, #0x300000 */ + .long 0xd5181040 /* msr cpacr_el1, x0 */ + .long 0xd2800000 /* mov x0, #0x0 */ + .long 0xb2630000 /* orr x0, x0, #0x20000000 */ + .long 0xd51c1100 /* msr hcr_el2, x0 */ + .long 0xd53c1100 /* mrs x0, hcr_el2 */ + .long 0xd2810000 /* mov x0, #0x800 */ + .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ + .long 0xd5181000 /* msr sctlr_el1, x0 */ + .long 0x910003e0 /* mov x0, sp */ + .long 0xd51c4100 /* msr sp_el1, x0 */ + .long 0xd53cc000 /* mrs x0, vbar_el2 */ + .long 0xd518c000 /* msr vbar_el1, x0 */ + .long 0xd2803a60 /* mov x0, #0x1d3 */ + .long 0xd51c4000 /* msr spsr_el2, x0 */ + .long 0x10000060 /* adr x0, 1d008158 */ + .long 0xd51c4020 /* msr elr_el2, x0 */ + .long 0xd69f03e0 /* eret */ +el1_mode: + b z_arm_reset +#endif /** * * @brief Reset vector @@ -47,8 +128,10 @@ GTEXT(z_arm_platform_init) * */ SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset) -SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) + + #if defined(CONFIG_AARCH32_ARMV8_R) + /* Check if we are starting in HYP mode */ mrs r0, cpsr and r0, r0, #MODE_MASK diff --git a/arch/arm/core/mmu/arm_mmu.c b/arch/arm/core/mmu/arm_mmu.c index f37b4354d4660fcdec2794a57f65bea87f7cecc9..7f8cf8ffcc11f9b6526cd18944e6f50b555705f5 100644 --- a/arch/arm/core/mmu/arm_mmu.c +++ b/arch/arm/core/mmu/arm_mmu.c @@ -34,6 +34,10 @@ #include #include "arm_mmu_priv.h" +#ifdef CONFIG_DCACHE +#include +#endif + LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); /* Level 1 page table: always required, must be 16k-aligned */ @@ -73,7 +77,7 @@ static const struct arm_mmu_flat_range mmu_zephyr_ranges[] = { .start = (uint32_t)_image_ram_start, .end = (uint32_t)_image_ram_end, .attrs = MT_NORMAL | MATTR_SHARED | - MPERM_R | MPERM_W | + MPERM_R | MPERM_W |MPERM_X | MATTR_CACHE_OUTER_WB_WA | MATTR_CACHE_INNER_WB_WA}, /* Mark text segment cacheable, read only and executable */ @@ -855,7 +859,9 @@ int z_arm_mmu_init(void) reg_val |= ARM_MMU_SCTLR_DCACHE_ENABLE_BIT; reg_val |= ARM_MMU_SCTLR_MMU_ENABLE_BIT; __set_SCTLR(reg_val); - +#ifdef CONFIG_DCACHE + arch_dcache_invd_all() ; +#endif return 0; } diff --git a/arch/arm/core/vector_table.ld b/arch/arm/core/vector_table.ld index 463e389de9fb7486ac4d8f8780b0a1588672174e..75019401d9514fcb3276454e6d8d25b61e4cd3c1 100644 --- a/arch/arm/core/vector_table.ld +++ b/arch/arm/core/vector_table.ld @@ -47,6 +47,11 @@ . = ALIGN( 0x80 ); #endif +aarch64_2_aarch32 = .; +KEEP(*(.aarch64_2_aarch32_section)) +KEEP(*(".aarch64_2_aarch32_section.*")) + +. = ALIGN( 0x80 ); _vector_start = .; KEEP(*(.exc_vector_table)) KEEP(*(".exc_vector_table.*")) diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 367480015c4b1f9f8cf357ed1508c7c0fc10a4cb..a5ad5ef1c45639f07067c93754e0283dadc995b7 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -30,6 +30,27 @@ config CPU_AARCH64_CORTEX_R help This option signifies the use of a CPU of the Cortex-R 64-bit family. +config CPU_PHYTIUM_FTC310 + bool + select CPU_CORTEX_A + select ARMV8_A + help + This option signifies the use of a Phytium-FTC310 CPU + +config CPU_PHYTIUM_FTC862 + bool + select CPU_CORTEX_A + select ARMV8_A + help + This option signifies the use of a Phytium-FTC862 CPU + +config CPU_PHYTIUM_FTC663 + bool + select CPU_CORTEX_A + select ARMV8_A + help + This option signifies the use of a Phytium-FTC664 CPU + config CPU_CORTEX_A53 bool select CPU_CORTEX_A @@ -218,6 +239,11 @@ config ARMV8_A so that it can support some features included in the AArch64 state. It supports the T32 and A32 instruction sets. +config USE_EL2 + bool "Use EL2 for kernel execution" + help + this option enables the use of EL2 for kernel execution + rsource "xen/Kconfig" endif # CPU_CORTEX_A diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index a02ae13acf89cae1308f95540cce5d54db35dc79..0b6878b118b270d64bcba74ed5851450022abb9a 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -322,6 +322,13 @@ void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf) far = read_far_el1(); elr = read_elr_el1(); break; +#ifdef CONFIG_USE_EL2 + case MODE_EL2: + esr = read_esr_el2(); + far = read_far_el2(); + elr = read_elr_el2(); + break; +#endif #if !defined(CONFIG_ARMV8_R) case MODE_EL3: esr = read_esr_el3(); diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c index f0abb4a029a690da98324784f0e7cabec53e4bf1..54b38f66364a91bff5df5af654f87fb27294a99f 100644 --- a/arch/arm64/core/mmu.c +++ b/arch/arm64/core/mmu.c @@ -686,9 +686,12 @@ static uint64_t get_region_desc(uint32_t attrs) case MT_NORMAL_NC: case MT_NORMAL: /* Make Normal RW memory as execute never */ - if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) - desc |= PTE_BLOCK_DESC_PXN; +#ifndef CONFIG_USE_EL2 + if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) + desc |= PTE_BLOCK_DESC_PXN; +#else +#endif if (((attrs & MT_RW) && (attrs & MT_RW_AP_ELx)) || (attrs & MT_U_EXECUTE_NEVER)) desc |= PTE_BLOCK_DESC_UXN; @@ -750,9 +753,16 @@ static void remove_map(struct arm_mmu_ptables *ptables, const char *name, static void invalidate_tlb_all(void) { - __asm__ volatile ( - "dsb ishst; tlbi vmalle1; dsb ish; isb" +#ifndef CONFIG_USE_EL2 +__asm__ volatile ( + "dsb ishst; tlbi vmalle1; dsb sy; isb" : : : "memory"); +#else +__asm__ volatile ( + "dsb ishst; tlbi alle2; dsb ish; isb" + : : : "memory"); +#endif + } /* zephyr execution regions with appropriate attributes */ @@ -773,7 +783,12 @@ static const struct arm_mmu_flat_range mmu_zephyr_ranges[] = { { .name = "zephyr_data", .start = _image_ram_start, .end = _image_ram_end, - .attrs = MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE }, +#ifndef CONFIG_USE_EL2 + .attrs = MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE , +#else + .attrs = MT_NORMAL | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE, +#endif + }, /* Mark text segment cacheable,read only and executable */ { .name = "zephyr_code", @@ -922,7 +937,7 @@ static uint64_t get_tcr(int el) return tcr; } - +#ifndef CONFIG_USE_EL2 static void enable_mmu_el1(struct arm_mmu_ptables *ptables, unsigned int flags) { ARG_UNUSED(flags); @@ -946,6 +961,30 @@ static void enable_mmu_el1(struct arm_mmu_ptables *ptables, unsigned int flags) MMU_DEBUG("MMU enabled with dcache\n"); } +#else +static void enable_mmu_el2(struct arm_mmu_ptables *ptables, unsigned int flags) +{ + ARG_UNUSED(flags); + uint64_t val; + + /* Set MAIR, TCR and TBBR registers */ + write_mair_el2(MEMORY_ATTRIBUTES); + write_tcr_el2(get_tcr(2)); + write_ttbr0_el2((uint64_t)ptables->base_xlat_table); + + /* Ensure these changes are seen before MMU is enabled */ + barrier_isync_fence_full(); + + /* Enable the MMU and data cache */ + val = read_sctlr_el2(); + write_sctlr_el2(val | SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT); + + /* Ensure the MMU enable takes effect immediately */ + barrier_isync_fence_full(); + + MMU_DEBUG("MMU enabled with dcache\n"); +} +#endif /* ARM MMU Driver Initial Setup */ static struct arm_mmu_ptables kernel_ptables; @@ -966,12 +1005,21 @@ void z_arm64_mm_init(bool is_primary_core) __ASSERT(CONFIG_MMU_PAGE_SIZE == KB(4), "Only 4K page size is supported\n"); - __ASSERT(GET_EL(read_currentel()) == MODE_EL1, - "Exception level not EL1, MMU not enabled!\n"); +#ifndef CONFIG_USE_EL2 + __ASSERT(GET_EL(read_currentel()) == MODE_EL1, + "Exception level not EL1, MMU not enabled!\n"); +#else + __ASSERT(GET_EL(read_currentel()) == MODE_EL2, + "Exception level not EL2, MMU not enabled!\n"); +#endif +#ifndef CONFIG_USE_EL2 + /* Ensure that MMU is already not enabled */ + __ASSERT((read_sctlr_el1() & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); +#else /* Ensure that MMU is already not enabled */ - __ASSERT((read_sctlr_el1() & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); - + __ASSERT((read_sctlr_el2() & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); +#endif /* * Only booting core setup up the page tables. */ @@ -980,8 +1028,12 @@ void z_arm64_mm_init(bool is_primary_core) setup_page_tables(&kernel_ptables); } - /* currently only EL1 is supported */ - enable_mmu_el1(&kernel_ptables, flags); +#ifndef CONFIG_USE_EL2 + /* currently only EL1 is supported */ + enable_mmu_el1(&kernel_ptables, flags); +#else + enable_mmu_el2(&kernel_ptables, flags) ; +#endif } static void sync_domains(uintptr_t virt, size_t size, const char *name) diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S index a01139ad70091654ac21135fa1097a8697690f40..970a7348264e4256f38c12184c0145ccc676f8a6 100644 --- a/arch/arm64/core/reset.S +++ b/arch/arm64/core/reset.S @@ -67,9 +67,15 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c) /* Custom plat prep_c init */ bl z_arm64_el2_plat_prep_c +#ifndef CONFIG_USE_EL2 /* Set SP_EL1 */ msr sp_el1, x24 - +#else + # msr sp_el2, x24 + msr SPSel, #1 + # use sp_el2 + mov sp, x24 +#endif b out 1: /* Disable alignment fault checking */ @@ -221,6 +227,7 @@ switch_el: 3: #if !defined(CONFIG_ARMV8_R) +#ifndef CONFIG_USE_EL2 /* EL3 init */ bl z_arm64_el3_init @@ -228,19 +235,88 @@ switch_el: adr x0, switch_el bl z_arm64_el3_get_next_el eret +#else + /* initialize sctlr_el2 and hcr_el2 to save values before entering el2.*/ + msr sctlr_el2, xzr + msr hcr_el2, xzr + /* determine the el2 execution state.*/ + mrs x0, scr_el3 + orr x0, x0, #(1<<10) + /* rw el2 execution state is aarch64.*/ + orr x0, x0, #(1<<0) + /* ns el1 is non-secure world.*/ + msr scr_el3, x0 + mov x0, #0b01001 + orr x0, x0, SPSR_DAIF_MASK + # orr x0, x0, SPSR_MODE_EL1T + /* daif=0000 */ + msr spsr_el3, x0 + /* m[4:0]=01001 el2h must match scr_el3.rw*/ + + # bl FTraceEL3 + /* determine el2 entry.*/ + adr x0, 2f + /* El2Entry points to the first instruction of */ + msr elr_el3, x0 + /* el2 code.*/ + eret +#endif #endif /* CONFIG_ARMV8_R */ 2: + mov sp, x24 /* EL2 init */ bl z_arm64_el2_init +#ifndef CONFIG_USE_EL2 /* Move to EL1 with all exceptions masked */ mov_imm x0, (SPSR_DAIF_MASK | SPSR_MODE_EL1T) msr spsr_el2, x0 + bl InvalidateFlushDcaches + dsb sy + isb + adr x0, 1f msr elr_el2, x0 + + mrs x1, HCR_EL2 + orr x1, x1, #(1<<31) + bic x1, x1, #(1<<27) /* HCR_EL2.TGE = 0 */ + bic x1, x1, #(1<<5) /* HCR_EL2.AMO = 0 */ + bic x1, x1, #(1<<4) /* HCR_EL2.IMO = 0 */ + bic x1, x1, #(1<<3) /* HCR_EL2.FMO = 0 */ + orr x1, x1, #(1<<1) /* HCR_EL2.SWIO = 1 */ + /* rw=1 el1 execution state is aarch64.*/ + msr HCR_EL2, x1 + isb + eret +#else + + msr sctlr_el2, xzr + isb + + ldr x0,=__hcr_set + ldr x0, [x0] + msr hcr_el2, x0 + mov x0,0 + msr CNTHCTL_EL2, x0 + bl InvalidateFlushDcaches + dsb sy + isb + + /* We want to use SP_ELx from now on */ + msr SPSel, #1 + + /* Enable SError interrupts */ + msr DAIFClr, #(DAIFCLR_ABT_BIT) + isb + + ret x25 + +#endif + 1: /* EL1 init */ @@ -254,3 +330,85 @@ switch_el: isb ret x25 /* either z_prep_c or z_arm64_secondary_prep_c */ + + +/* flush or invalidate dcache, refer to rt-thread __asm_flush_dcache_all */ +InvalidateFlushDcacheLevel: + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways, ccsidr_el1[12:3] */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets, ccsidr_el1[27:13] */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +InvalidateFlushCacheSet: + mov x6, x3 /* x6 <- working copy of #ways */ + +InvalidateFlushCacheWay: + lsl x7, x6, x5 /* x7 = x6 << x5 */ + orr x9, x12, x7 /* x9 = x12 | x7, map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f /* x1 = 0f, flush cache */ + dc isw, x9 /* invalidate dcache */ + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge InvalidateFlushCacheWay + subs x4, x4, #1 /* decrement the set */ + b.ge InvalidateFlushCacheSet + + ret + +.global InvalidateFlushDcaches +InvalidateFlushDcaches: + mov x1, x0 /* x1 = 0 flush, x1 = 1 invalidate */ + dsb sy /* barrier for full system */ + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc bit[26:24], level of cache hierarchy */ + cbz x11, InvalidateFlushDcacheEnd /* if loc is 0, no cache, exit */ + mov x15, lr /* preserve LR */ + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +InvalidateFlushCachesLoopLevel: + lsl x12, x0, #1 /* x12 = x0 * 2 */ + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 /* get x10, clidr_el1[ctype-n] to x12 */ + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 /* if not 000(no-cache), 001(i-cache only) */ + b.lt InvalidateFlushCachesSkipLevel /* skip if no cache or icache */ + bl InvalidateFlushDcacheLevel /* x1 = 0 flush, 1 invalidate */ + +InvalidateFlushCachesSkipLevel: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt InvalidateFlushCachesLoopLevel + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +InvalidateFlushDcacheEnd: + ret + + +.align 3 +__hcr_set: + .dword 0x38 diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c index 03cf389007d94987f083d97c4fe2c38d8893ac5c..54e62bc159f4d702bd2789ec31dd7298f5e6dd8b 100644 --- a/arch/arm64/core/reset.c +++ b/arch/arm64/core/reset.c @@ -121,6 +121,10 @@ void z_arm64_el2_init(void) { uint64_t reg; + write_vbar_el2((uint64_t)_vector_table); + barrier_isync_fence_full(); +#ifndef CONFIG_USE_EL2 + reg = read_sctlr_el2(); reg |= (SCTLR_EL2_RES1 | /* RES1 */ SCTLR_I_BIT | /* Enable i-cache */ @@ -142,7 +146,23 @@ void z_arm64_el2_init(void) reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */ CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */ write_cptr_el2(reg); +#else + + reg = 0U; /* RES0 */ + reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP initially */ + /* TODO: CONFIG_FLOAT_*_FORBIDDEN */ + write_cpacr_el1(reg); + + reg = read_sctlr_el2(); + reg |= (SCTLR_EL2_RES1 | /* RES1 */ + SCTLR_I_BIT | /* Enable i-cache */ + SCTLR_C_BIT | /* Enable d-cache */ + SCTLR_SA_BIT); /* Enable SP alignment check */ + write_sctlr_el1(reg); + write_cntv_cval_el0(~(uint64_t)0); + +#endif zero_cntvoff_el2(); /* Set 64-bit virtual timer offset to 0 */ zero_cnthctl_el2(); #ifdef CONFIG_CPU_AARCH64_CORTEX_R @@ -208,6 +228,7 @@ void z_arm64_el3_get_next_el(uint64_t switch_addr) /* Mask the DAIF */ spsr = SPSR_DAIF_MASK; +#ifndef CONFIG_USE_EL2 if (el3_get_next_el() == EL3_TO_EL2) { /* Dropping into EL2 */ spsr |= SPSR_MODE_EL2T; @@ -215,6 +236,9 @@ void z_arm64_el3_get_next_el(uint64_t switch_addr) /* Dropping into EL1 */ spsr |= SPSR_MODE_EL1T; } +#else + spsr |= SPSR_MODE_EL2T; +#endif write_spsr_el3(spsr); } diff --git a/arch/arm64/core/switch.S b/arch/arm64/core/switch.S index 333b8f0b21e35254444f7f21558350352ec26574..a436cfa1a3e5f46a6047cc9a793a1ed5c5927e56 100644 --- a/arch/arm64/core/switch.S +++ b/arch/arm64/core/switch.S @@ -141,8 +141,15 @@ SECTION_FUNC(TEXT, z_arm64_context_switch) GTEXT(z_arm64_sync_exc) SECTION_FUNC(TEXT, z_arm64_sync_exc) +#ifndef CONFIG_USE_EL2 mrs x0, esr_el1 lsr x1, x0, #26 +#else + mrs x0, esr_el2 + lsr x1, x0, #26 +#endif + + #ifdef CONFIG_FPU_SHARING cmp x1, #0x07 /*Access to SIMD or floating-point */ diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index 18f49945eda4959d231384658fd103b337bb12cb..5a9c83a6e781f0b518aaa9162532221a03f452bf 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -130,9 +130,13 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, pInitCtx->elr = (uint64_t)z_thread_entry; #endif +#ifndef CONFIG_USE_EL2 /* Keep using SP_EL1 */ pInitCtx->spsr = SPSR_MODE_EL1H | DAIF_FIQ_BIT; - +#else + /* Keep using SP_EL1 */ + pInitCtx->spsr = SPSR_MODE_EL2H | DAIF_FIQ_BIT; +#endif /* thread birth happens through the exception return path */ thread->arch.exception_depth = 1; diff --git a/arch/arm64/core/vector_table.S b/arch/arm64/core/vector_table.S index 632304b70299ee84acc68759951f4dbf39dd75e3..fa90c0eb6be3e0297263cd80f12741647a8a4f51 100644 --- a/arch/arm64/core/vector_table.S +++ b/arch/arm64/core/vector_table.S @@ -76,9 +76,15 @@ _ASM_FILE_PROLOGUE str x29, [sp, ___esf_t_fp_OFFSET] #endif +#ifndef CONFIG_USE_EL2 mrs \xreg0, spsr_el1 mrs \xreg1, elr_el1 stp \xreg0, \xreg1, [sp, ___esf_t_spsr_elr_OFFSET] +#else + mrs \xreg0, spsr_el2 + mrs \xreg1, elr_el2 + stp \xreg0, \xreg1, [sp, ___esf_t_spsr_elr_OFFSET] +#endif #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK .if \el == el0 @@ -152,12 +158,20 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) /* Current EL with SP0 / Synchronous */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif b z_arm64_sync_exc /* Current EL with SP0 / IRQ */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif #ifdef CONFIG_GEN_SW_ISR_TABLE b _isr_wrapper #else @@ -170,17 +184,29 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) /* Current EL with SP0 / SError */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif b z_arm64_serror /* Current EL with SPx / Synchronous */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif b z_arm64_sync_exc /* Current EL with SPx / IRQ */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif #ifdef CONFIG_GEN_SW_ISR_TABLE b _isr_wrapper #else @@ -193,7 +219,11 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) /* Current EL with SPx / SError */ .align 7 +#ifndef CONFIG_USE_EL2 z_arm64_enter_exc x0, x1, el1 +#else + z_arm64_enter_exc x0, x1, el2 +#endif b z_arm64_serror /* Lower EL using AArch64 / Synchronous */ @@ -309,8 +339,14 @@ SECTION_FUNC(TEXT, z_arm64_exit_exc) #endif ldp x0, x1, [sp, ___esf_t_spsr_elr_OFFSET] + +#ifndef CONFIG_USE_EL2 msr spsr_el1, x0 msr elr_el1, x1 +#else + msr spsr_el2, x0 + msr elr_el2, x1 +#endif /* Restore the kernel/user mode flag and decrement exception depth */ tst x0, #SPSR_MODE_MASK /* EL0 == 0 */ diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index f1a40a8b318726c3f4f8712c642527803ebd3725..01d6d40e215b4853909f3d80bb017536f96b5000 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -902,3 +902,87 @@ set(xiao_esp32s3_DEPRECATED set(yd_esp32_DEPRECATED yd_esp32/esp32/procpu ) + +set(e2000d_demo_smp_DEPRECATED + e2000d_demo/pe2202/smp +) + +set(e2000d_demo_el2_DEPRECATED + e2000d_demo/pe2202/el2 +) + +set(e2000d_demo_el2_smp_DEPRECATED + e2000d_demo/pe2202/el2/smp +) + +set(e2000q_demo_smp_DEPRECATED + e2000q_demo/pe2204/smp +) + +set(e2000q_demo_el2_DEPRECATED + e2000q_demo/pe2204/el2 +) + +set(e2000q_demo_el2_smp_DEPRECATED + e2000q_demo/pe2204/el2/smp +) + +set(d2000_demo_smp_DEPRECATED + d2000_demo/pd2008/smp +) + +set(d2000_demo_el2_DEPRECATED + d2000_demo/pd2008/el2 +) + +set(d2000_demo_el2_smp_DEPRECATED + d2000_demo/pd2008/el2/smp +) + +set(pd2308_demo_smp_DEPRECATED + pd2308_demo/pd2308/smp +) + +set(pd2308_demo_el2_DEPRECATED + pd2308_demo/pd2308/el2 +) + +set(pd2308_demo_el2_smp_DEPRECATED + pd2308_demo/pd2308/el2/smp +) + +set(ps2316_test_smp_DEPRECATED + ps2316_test/ps2316/smp +) + +set(ps2316_test_el2_DEPRECATED + ps2316_test/ps2316/el2 +) + +set(ps2316_test_el2_smp_DEPRECATED + ps2316_test/ps2316/el2/smp +) + +set(pd2408_test_a_smp_DEPRECATED + pd2408_test_a/pd2408/smp +) + +set(pd2408_test_a_el2_DEPRECATED + pd2408_test_a/pd2408/el2 +) + +set(pd2408_test_a_el2_smp_DEPRECATED + pd2408_test_a/pd2408/el2/smp +) + +set(pd2408_test_b_smp_DEPRECATED + pd2408_test_b/pd2408/smp +) + +set(pd2408_test_b_el2_DEPRECATED + pd2408_test_b/pd2408/el2 +) + +set(pd2408_test_b_el2_smp_DEPRECATED + pd2408_test_b/pd2408/el2/smp +) diff --git a/boards/phytium/d2000_aarch32_demo/Kconfig.d2000_aarch32_demo b/boards/phytium/d2000_aarch32_demo/Kconfig.d2000_aarch32_demo new file mode 100644 index 0000000000000000000000000000000000000000..ffc4c7cf90784a0a43ecb5a5009ec076fef81957 --- /dev/null +++ b/boards/phytium/d2000_aarch32_demo/Kconfig.d2000_aarch32_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_D2000_AARCH32_DEMO + bool "phytium D2000 aarch32" + select SOC_PD2008_AARCH32 \ No newline at end of file diff --git a/boards/phytium/d2000_aarch32_demo/Kconfig.defconfig b/boards/phytium/d2000_aarch32_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..d1a8a2332908ea6f00b16c1746a712e7d1fe0eaa --- /dev/null +++ b/boards/phytium/d2000_aarch32_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium d2000 aarch32 demo" + depends on BOARD_D2000_AARCH32_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/d2000_aarch32_demo/board.cmake b/boards/phytium/d2000_aarch32_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/d2000_aarch32_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/d2000_aarch32_demo/board.yml b/boards/phytium/d2000_aarch32_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..27eaf1b2255e67248b49ad1fa9047d7cb7a15f2a --- /dev/null +++ b/boards/phytium/d2000_aarch32_demo/board.yml @@ -0,0 +1,6 @@ +board: + name: d2000_aarch32_demo + vendor: phytium + socs: + - name: pd2008_aarch32 + diff --git a/boards/phytium/d2000_aarch32_demo/d2000_aarch32_demo_defconfig b/boards/phytium/d2000_aarch32_demo/d2000_aarch32_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..a96402d4b33218ff2af4acadbe0a6eeb1aa61892 --- /dev/null +++ b/boards/phytium/d2000_aarch32_demo/d2000_aarch32_demo_defconfig @@ -0,0 +1,20 @@ +CONFIG_SOC_PD2008_AARCH32=y +CONFIG_BOARD_D2000_AARCH32_DEMO=y + + +# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) +CONFIG_ARM_ARCH_TIMER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 + +#CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +CONFIG_ARM_MMU_NUM_L2_TABLES=1024 + + +CONFIG_ARMV7_SYS_STACK_SIZE=8192 +# 主堆栈的大小 +CONFIG_MAIN_STACK_SIZE=8192 \ No newline at end of file diff --git a/boards/phytium/d2000_demo/Kconfig.d2000_demo b/boards/phytium/d2000_demo/Kconfig.d2000_demo new file mode 100644 index 0000000000000000000000000000000000000000..8f7b2d81780ae31f3c47c6b07f877f57885e0e78 --- /dev/null +++ b/boards/phytium/d2000_demo/Kconfig.d2000_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_D2000_DEMO + bool "phytium d2000" + select SOC_PD2008 diff --git a/boards/phytium/d2000_demo/Kconfig.defconfig b/boards/phytium/d2000_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..4285db2362084ce8c2761375cfbb966aa4d75eab --- /dev/null +++ b/boards/phytium/d2000_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium d2000 demo" + depends on BOARD_D2000_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/d2000_demo/board.cmake b/boards/phytium/d2000_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/d2000_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/d2000_demo/board.yml b/boards/phytium/d2000_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..4e0dfb7613598f00c83763041015c42dcd4ec9fd --- /dev/null +++ b/boards/phytium/d2000_demo/board.yml @@ -0,0 +1,10 @@ +board: + name: d2000_demo + vendor: phytium + socs: + - name: pd2008 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/d2000_demo/d2000_demo.yaml b/boards/phytium/d2000_demo/d2000_demo.yaml new file mode 100644 index 0000000000000000000000000000000000000000..88ef06e759fd185376d22cf1221e056871ee49a3 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo.yaml @@ -0,0 +1,7 @@ +identifier: d2000_demo +name: Phytium d2000 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_defconfig b/boards/phytium/d2000_demo/d2000_demo_pd2008_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..23ad632a79648237f8da659bb690ce99d53c4962 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=8192 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_el2.yaml b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0d345a6812a1b1c226de33e909764d10832cacc8 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2.yaml @@ -0,0 +1,7 @@ +identifier: d2000_demo/d2000/el2 +name: Phytium d2000 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_defconfig b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp.yaml b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8eb762aa7d802bb3655b0580445a9d5dcd0edc0e --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: d2000_demo/d2000/el2/smp +name: Phytium d2000 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp_defconfig b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e066e47dbe5043d7b0dee65f91c55411797e08c3 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_smp.yaml b/boards/phytium/d2000_demo/d2000_demo_pd2008_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c75ca49b3e26a46fd4616a3f21b53531cb9d4029 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_smp.yaml @@ -0,0 +1,9 @@ +identifier: d2000_demo/d2000/smp +name: Phytium d2000 demo smp +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp \ No newline at end of file diff --git a/boards/phytium/d2000_demo/d2000_demo_pd2008_smp_defconfig b/boards/phytium/d2000_demo/d2000_demo_pd2008_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2896228ec7ea3cb6f57507d066e02b9a02b5d8a8 --- /dev/null +++ b/boards/phytium/d2000_demo/d2000_demo_pd2008_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/boards/phytium/e2000d_aarch32_demo/Kconfig.defconfig b/boards/phytium/e2000d_aarch32_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..185d900eb3efcebb48555da1e89929ba3511505a --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium e2000d aarch32 demo" + depends on BOARD_E2000D_A32_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/e2000d_aarch32_demo/Kconfig.e2000d_aarch32_demo b/boards/phytium/e2000d_aarch32_demo/Kconfig.e2000d_aarch32_demo new file mode 100644 index 0000000000000000000000000000000000000000..1f81e5ab921422ef7feffe21d726e2d49ff66766 --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/Kconfig.e2000d_aarch32_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_E2000D_AARCH32_DEMO + bool "phytium e2000d aarch32" + select SOC_PE2202_AARCH32 \ No newline at end of file diff --git a/boards/phytium/e2000d_aarch32_demo/board.cmake b/boards/phytium/e2000d_aarch32_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000d_aarch32_demo/board.yml b/boards/phytium/e2000d_aarch32_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..783de4876ba9860900b570158ab39e12666c6562 --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/board.yml @@ -0,0 +1,5 @@ +board: + name: e2000d_aarch32_demo + vendor: phytium + socs: + - name: pe2202_aarch32 diff --git a/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo.dts b/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo.dts new file mode 100644 index 0000000000000000000000000000000000000000..4c88b749bdaf13c334e14539a083481c5bf3864a --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "Phytium e2000d aarch32 demo"; + compatible = "phytium,e2000d-demo", "phytium,e2000d"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; \ No newline at end of file diff --git a/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo_defconfig b/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..f5172782954443c55620a35d4d0db23c0c1748b2 --- /dev/null +++ b/boards/phytium/e2000d_aarch32_demo/e2000d_aarch32_demo_defconfig @@ -0,0 +1,20 @@ +CONFIG_SOC_PE2202_AARCH32=y +CONFIG_BOARD_E2000D_AARCH32_DEMO=y + + +# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) +CONFIG_ARM_ARCH_TIMER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 + +#CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +CONFIG_ARM_MMU_NUM_L2_TABLES=1024 + + +CONFIG_ARMV7_SYS_STACK_SIZE=8192 +# 主堆栈的大小 +CONFIG_MAIN_STACK_SIZE=8192 \ No newline at end of file diff --git a/boards/phytium/e2000d_demo/CMakeLists.txt b/boards/phytium/e2000d_demo/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000d_demo/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000d_demo/Kconfig.defconfig b/boards/phytium/e2000d_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..ec8be524969605196245101f61c36cae5a192b80 --- /dev/null +++ b/boards/phytium/e2000d_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium e2000d demo" + depends on BOARD_E2000D_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/e2000d_demo/Kconfig.e2000d_demo b/boards/phytium/e2000d_demo/Kconfig.e2000d_demo new file mode 100644 index 0000000000000000000000000000000000000000..3a72cf44d2699341296efcac2315e586ac6e0880 --- /dev/null +++ b/boards/phytium/e2000d_demo/Kconfig.e2000d_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_E2000D_DEMO + bool "phytium e2000d" + select SOC_PE2202 diff --git a/boards/phytium/e2000d_demo/board.cmake b/boards/phytium/e2000d_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000d_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000d_demo/board.yml b/boards/phytium/e2000d_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..05d11e269b727bf2ed09413012f14fc32b4a636e --- /dev/null +++ b/boards/phytium/e2000d_demo/board.yml @@ -0,0 +1,12 @@ +board: + name: e2000d_demo + vendor: phytium + socs: + - name: pe2202 + variants: + - name: smp + - name: el2 + variants: + - name: smp + + diff --git a/boards/phytium/e2000d_demo/e2000d_demo.dts b/boards/phytium/e2000d_demo/e2000d_demo.dts new file mode 100644 index 0000000000000000000000000000000000000000..a909f11309e42cac34ac31d2363be595872daade --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "e2000d_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000d demo"; + compatible = "phytium,e2000d-demo", "phytium,e2000d"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc0 { + status = "okay"; + emmc { + compatible = "zephyr,emmc-disk"; + status = "okay"; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; \ No newline at end of file diff --git a/boards/phytium/e2000d_demo/e2000d_demo.yaml b/boards/phytium/e2000d_demo/e2000d_demo.yaml new file mode 100644 index 0000000000000000000000000000000000000000..636d8bc87cf60c1ebdaeb90a51f4c846367ec552 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo.yaml @@ -0,0 +1,7 @@ +identifier: e2000d_demo +name: Phytium e2000d demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/e2000d_demo/e2000d_demo_defconfig b/boards/phytium/e2000d_demo/e2000d_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..1e8c182d8ff2dfc21c70ccefdcbbf511be9b629f --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.dts b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.dts new file mode 100644 index 0000000000000000000000000000000000000000..ef8d6b06bba338d1cba43d945b2577457baeb293 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "e2000d_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000d demo"; + compatible = "phytium,e2000d-demo", "phytium,e2000d"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; \ No newline at end of file diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.yaml b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..87ca6dcdb61eed177287af67ca153d628f61fb73 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2.yaml @@ -0,0 +1,7 @@ +identifier: e2000d_demo/e2000d/el2 +name: Phytium e2000d demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_defconfig b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..01601d8dd9c3a4af7b2ae0b9a23ee29d13eef64e --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# el2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.dts b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.dts new file mode 100644 index 0000000000000000000000000000000000000000..5aa64e45aa5836732ce993003286d90c721a7886 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "e2000d_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000d demo"; + compatible = "phytium,e2000d-demo", "phytium,e2000d"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.yaml b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..90093797e21805597d3937d27c7785ce266e87bb --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: e2000d_demo/e2000d/el2/smp +name: Phytium e2000d demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp_defconfig b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..caa1af3329f15131c3a59adb7e5569084f3f1234 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.dts b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.dts new file mode 100644 index 0000000000000000000000000000000000000000..d26e3c6ecf108695131a15e446730f5eb54808b4 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "e2000d_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000d demo"; + compatible = "phytium,e2000d-demo", "phytium,e2000d"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.yaml b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a983077654cd42a032e6c6fa96ddacfce5a365e4 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp.yaml @@ -0,0 +1,9 @@ +identifier: e2000d_demo/e2000d/smp +name: Phytium e2000d demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp_defconfig b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..50ea07918d638ecce442a13733387ed4921176e5 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pe2202_smp_defconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + diff --git a/boards/phytium/e2000d_demo/e2000d_demo_pinctrl.dtsi b/boards/phytium/e2000d_demo/e2000d_demo_pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cb1fd77213bf3daf54c6215a5603afe3247558d2 --- /dev/null +++ b/boards/phytium/e2000d_demo/e2000d_demo_pinctrl.dtsi @@ -0,0 +1,19 @@ + + +#include + +&pinctrl { + uart1_rx_default: uart1_rx_default { + pinmux = ; + }; + uart1_tx_default: uart1_tx_default { + pinmux = ; + }; + + uart2_rx_default: uart2_rx_default { + pinmux = ; + }; + uart2_tx_default: uart2_tx_default { + pinmux = ; + }; +}; \ No newline at end of file diff --git a/boards/phytium/e2000q_aarch32_demo/Kconfig.defconfig b/boards/phytium/e2000q_aarch32_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..cf6ae0db201603ab56c7f22f130106cf6356ee99 --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium e2000q aarch32 demo" + depends on BOARD_E2000Q_AARCH32_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/e2000q_aarch32_demo/Kconfig.e2000q_aarch32_demo b/boards/phytium/e2000q_aarch32_demo/Kconfig.e2000q_aarch32_demo new file mode 100644 index 0000000000000000000000000000000000000000..6706147b5605fd9f01cd345c33e6480bf4069f52 --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/Kconfig.e2000q_aarch32_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_E2000Q_AARCH32_DEMO + bool "phytium e2000q aarch32" + select SOC_PE2204_AARCH32 \ No newline at end of file diff --git a/boards/phytium/e2000q_aarch32_demo/board.cmake b/boards/phytium/e2000q_aarch32_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000q_aarch32_demo/board.yml b/boards/phytium/e2000q_aarch32_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..ccba83529ee945e215b47d3ee067a83a92c51455 --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/board.yml @@ -0,0 +1,5 @@ +board: + name: e2000q_aarch32_demo + vendor: phytium + socs: + - name: pe2204_aarch32 diff --git a/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo.dts b/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo.dts new file mode 100644 index 0000000000000000000000000000000000000000..7b0eb4d46d3b3a12e90654ebb636815bd2a9aafa --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "Phytium e2000q demo"; + compatible = "phytium,e2000q-demo", "phytium,e2000q"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + zephyr,pcie-controller = &pcie0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo_defconfig b/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..f8ded46085d5286fed92a36f33b476c10fa5a94d --- /dev/null +++ b/boards/phytium/e2000q_aarch32_demo/e2000q_aarch32_demo_defconfig @@ -0,0 +1,20 @@ +CONFIG_SOC_PE2204_AARCH32=y +CONFIG_BOARD_E2000Q_AARCH32_DEMO=y + + +# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) +CONFIG_ARM_ARCH_TIMER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 + +#CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +CONFIG_ARM_MMU_NUM_L2_TABLES=1024 + + +CONFIG_ARMV7_SYS_STACK_SIZE=8192 +# 主堆栈的大小 +CONFIG_MAIN_STACK_SIZE=8192 \ No newline at end of file diff --git a/boards/phytium/e2000q_demo/CMakeLists.txt b/boards/phytium/e2000q_demo/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000q_demo/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000q_demo/Kconfig.defconfig b/boards/phytium/e2000q_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..c91698970a1e651a98e5cc2c046af5d9d4fa57d0 --- /dev/null +++ b/boards/phytium/e2000q_demo/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium e2000q demo" + depends on BOARD_E2000Q_DEMO + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/e2000q_demo/Kconfig.e2000q_demo b/boards/phytium/e2000q_demo/Kconfig.e2000q_demo new file mode 100644 index 0000000000000000000000000000000000000000..154f282ec1322f99f6337b66baed62a2d423c908 --- /dev/null +++ b/boards/phytium/e2000q_demo/Kconfig.e2000q_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_E2000Q_DEMO + bool "phytium e2000q demo" + select SOC_PE2204 diff --git a/boards/phytium/e2000q_demo/board.cmake b/boards/phytium/e2000q_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/e2000q_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/e2000q_demo/board.yml b/boards/phytium/e2000q_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..f1a589959f65feb1e04b64bb0c07cff0067ec3a1 --- /dev/null +++ b/boards/phytium/e2000q_demo/board.yml @@ -0,0 +1,10 @@ +board: + name: e2000q_demo + vendor: phytium + socs: + - name: pe2204 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/e2000q_demo/e2000q_demo.dts b/boards/phytium/e2000q_demo/e2000q_demo.dts new file mode 100644 index 0000000000000000000000000000000000000000..baaa0dce37040e51f25f257739a2a48f68aab614 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo.dts @@ -0,0 +1,62 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "e2000q_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000q demo"; + compatible = "phytium,e2000q-demo", "phytium,e2000q"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + zephyr,pcie-controller = &pcie0; + }; +}; + +&sdhc0 { + status = "okay"; + emmc { + compatible = "zephyr,emmc-disk"; + status = "okay"; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_rx_default &uart2_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000q_demo/e2000q_demo.yaml b/boards/phytium/e2000q_demo/e2000q_demo.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7485efceea0c43e8017f7620e3fe27c1c04d9b16 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo.yaml @@ -0,0 +1,9 @@ +identifier: e2000q_demo +name: Phytium e2000q demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - netif:eth diff --git a/boards/phytium/e2000q_demo/e2000q_demo_defconfig b/boards/phytium/e2000q_demo/e2000q_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..1e8c182d8ff2dfc21c70ccefdcbbf511be9b629f --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.dts b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.dts new file mode 100644 index 0000000000000000000000000000000000000000..c021b5097ec49863c19e9f725dc22f353cf63f1e --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "e2000q_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000q demo"; + compatible = "phytium,e2000q-demo", "phytium,e2000q"; + #address-cells = <2>; + #size-cells = <2>; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + zephyr,pcie-controller = &pcie0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_rx_default &uart2_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.yaml b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..67be2b381d42fd51bf2419a093775113b6e3d658 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2.yaml @@ -0,0 +1,7 @@ +identifier: e2000q_demo/e2000q/el2 +name: Phytium e2000q demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_defconfig b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.dts b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.dts new file mode 100644 index 0000000000000000000000000000000000000000..1520fc809c30bb101456bc2e3e5d71b81e0444ac --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "e2000q_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000q demo"; + compatible = "phytium,e2000q-demo", "phytium,e2000q"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.yaml b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..84cf27eb3aca47412c93f395b5caefbf01a4799f --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: e2000q_demo/e2000q/el2/smp +name: Phytium e2000q demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp_defconfig b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..c03c4c25d26503b83e2444e929cabe16f27cbe2f --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.dts b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.dts new file mode 100644 index 0000000000000000000000000000000000000000..1520fc809c30bb101456bc2e3e5d71b81e0444ac --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2024 zhangyan + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "e2000q_demo_pinctrl.dtsi" + +/ { + model = "Phytium e2000q demo"; + compatible = "phytium,e2000q-demo", "phytium,e2000q"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + }; +}; + +&sdhc1 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; +}; + +&xmac0 { + status = "okay"; + local-mac-address = [00 00 00 01 02 03]; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.yaml b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4b9ff667a37c5af4db92913f8a234c63600db4d6 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp.yaml @@ -0,0 +1,9 @@ +identifier: e2000q_demo/e2000q/smp +name: Phytium e2000q demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp_defconfig b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..20660c4b1d2c53f6cda410fe3dd12d196db0e63f --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pe2204_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/boards/phytium/e2000q_demo/e2000q_demo_pinctrl.dtsi b/boards/phytium/e2000q_demo/e2000q_demo_pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3fedac477b072445dcef4cb8e8c15d636746a598 --- /dev/null +++ b/boards/phytium/e2000q_demo/e2000q_demo_pinctrl.dtsi @@ -0,0 +1,19 @@ + + +#include + +&pinctrl { + uart1_rx_default: uart1_rx_default { + pinmux = ; + }; + uart1_tx_default: uart1_tx_default { + pinmux = ; + }; + + uart2_rx_default: uart2_rx_default { + pinmux = ; + }; + uart2_tx_default: uart2_tx_default { + pinmux = ; + }; +}; \ No newline at end of file diff --git a/boards/phytium/index.rst b/boards/phytium/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..0595bf5712242826aa8695f4e6c34eaf57319fe1 --- /dev/null +++ b/boards/phytium/index.rst @@ -0,0 +1,10 @@ +.. _boards-aspeed: + +PHYTIUM +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/phytium/pd2308_demo/Kconfig.defconfig b/boards/phytium/pd2308_demo/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2b4010884f23a0a85de5f6596a25fdc214a73fed --- /dev/null +++ b/boards/phytium/pd2308_demo/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium pd2308 demo" + depends on BOARD_PD2308_DEMO diff --git a/boards/phytium/pd2308_demo/Kconfig.pd2308_demo b/boards/phytium/pd2308_demo/Kconfig.pd2308_demo new file mode 100644 index 0000000000000000000000000000000000000000..52cdef8f728f9be83824ac84b115c53689b48007 --- /dev/null +++ b/boards/phytium/pd2308_demo/Kconfig.pd2308_demo @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_PD2308_DEMO + bool "phytium pd2308" + select SOC_PD2308 diff --git a/boards/phytium/pd2308_demo/board.cmake b/boards/phytium/pd2308_demo/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/pd2308_demo/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/pd2308_demo/board.yml b/boards/phytium/pd2308_demo/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..12f77f776c553d8b18dd7cdfbe4326a3ceb544c6 --- /dev/null +++ b/boards/phytium/pd2308_demo/board.yml @@ -0,0 +1,10 @@ +board: + name: pd2308_demo + vendor: phytium + socs: + - name: pd2308 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/pd2308_demo/pd2308_demo.yaml b/boards/phytium/pd2308_demo/pd2308_demo.yaml new file mode 100644 index 0000000000000000000000000000000000000000..298f3851447d55a48c8ce6eeaecee781f3fe70c1 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo.yaml @@ -0,0 +1,7 @@ +identifier: pd2308_demo +name: Phytium pd2308 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2308_demo/pd2308_demo_defconfig b/boards/phytium/pd2308_demo/pd2308_demo_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..23ad632a79648237f8da659bb690ce99d53c4962 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=8192 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2.yaml b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f9e61c554576adedaa7ff7272b3f26be865f5bdc --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2.yaml @@ -0,0 +1,7 @@ +identifier: pd2308_demo/pd2308/el2 +name: Phytium d2000 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_defconfig b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp.yaml b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4dbd7da1a8fb360482b15ed4acecafb05e2bfa83 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2308_demo/pd2308/el2/smp +name: Phytium pd2308 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp_defconfig b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e066e47dbe5043d7b0dee65f91c55411797e08c3 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp.yaml b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..093f834e85eac5856a6684ecf69c4cf26f692919 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2308_demo/pd2308/smp +name: Phytium pd2308 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp \ No newline at end of file diff --git a/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp_defconfig b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2896228ec7ea3cb6f57507d066e02b9a02b5d8a8 --- /dev/null +++ b/boards/phytium/pd2308_demo/pd2308_demo_pd2308_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/boards/phytium/pd2408_test_a/Kconfig.defconfig b/boards/phytium/pd2408_test_a/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..d3f80b486166f00e2962db34c5524d40112ad4d2 --- /dev/null +++ b/boards/phytium/pd2408_test_a/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium pd2408 test a" + depends on BOARD_PD2408_TEST_A + +if NETWORKING +config NET_L2_ETHERNET + default y +endif # NETWORKING diff --git a/boards/phytium/pd2408_test_a/Kconfig.pd2408_test_a b/boards/phytium/pd2408_test_a/Kconfig.pd2408_test_a new file mode 100644 index 0000000000000000000000000000000000000000..01c209b5b64c576d286bb163b4464e887625e723 --- /dev/null +++ b/boards/phytium/pd2408_test_a/Kconfig.pd2408_test_a @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_PD2408_TEST_A + bool "phytium pd2408" + select SOC_PD2408 diff --git a/boards/phytium/pd2408_test_a/board.cmake b/boards/phytium/pd2408_test_a/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/pd2408_test_a/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/pd2408_test_a/board.yml b/boards/phytium/pd2408_test_a/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..868e2d9cf3f8b5681994a17a065009ba46318742 --- /dev/null +++ b/boards/phytium/pd2408_test_a/board.yml @@ -0,0 +1,10 @@ +board: + name: pd2408_test_a + vendor: phytium + socs: + - name: pd2408 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a.yaml b/boards/phytium/pd2408_test_a/pd2408_test_a.yaml new file mode 100644 index 0000000000000000000000000000000000000000..bd83dc786cb1f4703383bcff635314294f46c6d4 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a.yaml @@ -0,0 +1,7 @@ +identifier: pd2408_test_a +name: Phytium pd2408 test a +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_defconfig b/boards/phytium/pd2408_test_a/pd2408_test_a_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..23ad632a79648237f8da659bb690ce99d53c4962 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=8192 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2.yaml b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3a8d9cc95a7eb9c15bc867952e95a1aaec5c9f24 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2.yaml @@ -0,0 +1,7 @@ +identifier: pd2408_demo/pd2408/el2 +name: Phytium pd2408 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_defconfig b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp.yaml b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a334fe4e5aa54a695b424ff652b9eecb9eb16dfe --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2408_test_a/pd2408/el2/smp +name: Phytium pd2408 test a +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp_defconfig b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e066e47dbe5043d7b0dee65f91c55411797e08c3 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp.yaml b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a76019e132c365ad2b1eb5f5a2beed1938649434 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2408_test_a/pd2408/smp +name: Phytium pd2408 test a +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp \ No newline at end of file diff --git a/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp_defconfig b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2896228ec7ea3cb6f57507d066e02b9a02b5d8a8 --- /dev/null +++ b/boards/phytium/pd2408_test_a/pd2408_test_a_pd2408_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/boards/phytium/pd2408_test_b/Kconfig.defconfig b/boards/phytium/pd2408_test_b/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6f3f778c588e547cc0b27bb24478bf6272a2db98 --- /dev/null +++ b/boards/phytium/pd2408_test_b/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium pd2408 test b" + depends on BOARD_PD2408_TEST_B + +if NETWORKING +config NET_L2_ETHERNET + default y +endif # NETWORKING diff --git a/boards/phytium/pd2408_test_b/Kconfig.pd2408_test_b b/boards/phytium/pd2408_test_b/Kconfig.pd2408_test_b new file mode 100644 index 0000000000000000000000000000000000000000..72a341186cb83dc151ae2a01190a30b0d0714fd6 --- /dev/null +++ b/boards/phytium/pd2408_test_b/Kconfig.pd2408_test_b @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_PD2408_TEST_B + bool "phytium pd2408" + select SOC_PD2408 diff --git a/boards/phytium/pd2408_test_b/board.cmake b/boards/phytium/pd2408_test_b/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/pd2408_test_b/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/pd2408_test_b/board.yml b/boards/phytium/pd2408_test_b/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..1ef7a9e7a61d23db92d9b5ce9652954746591921 --- /dev/null +++ b/boards/phytium/pd2408_test_b/board.yml @@ -0,0 +1,10 @@ +board: + name: pd2408_test_b + vendor: phytium + socs: + - name: pd2408 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b.yaml b/boards/phytium/pd2408_test_b/pd2408_test_b.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ec68f42cd95f1ad567077200dae0108855da1309 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b.yaml @@ -0,0 +1,7 @@ +identifier: pd2408_test_b +name: Phytium pd2408 test b +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_defconfig b/boards/phytium/pd2408_test_b/pd2408_test_b_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..23ad632a79648237f8da659bb690ce99d53c4962 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=8192 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2.yaml b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3a8d9cc95a7eb9c15bc867952e95a1aaec5c9f24 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2.yaml @@ -0,0 +1,7 @@ +identifier: pd2408_demo/pd2408/el2 +name: Phytium pd2408 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_defconfig b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp.yaml b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7b136e46b134a1de94416a270da38cb504f48436 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2408_test_b/pd2408/el2/smp +name: Phytium pd2408 test b +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp_defconfig b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e066e47dbe5043d7b0dee65f91c55411797e08c3 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp.yaml b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fbb6c3926d7a231965013dbb1eef4d7ab2668ae9 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp.yaml @@ -0,0 +1,9 @@ +identifier: pd2408_test_b/pd2408/smp +name: Phytium pd2408 test b +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp \ No newline at end of file diff --git a/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp_defconfig b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2896228ec7ea3cb6f57507d066e02b9a02b5d8a8 --- /dev/null +++ b/boards/phytium/pd2408_test_b/pd2408_test_b_pd2408_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/boards/phytium/ps2316_test/Kconfig.defconfig b/boards/phytium/ps2316_test/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..0622550fb69e8d85a80f57a156129934f5a19e3a --- /dev/null +++ b/boards/phytium/ps2316_test/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + + +config BOARD + default "Phytium ps2316 test" + depends on BOARD_PS2316_TEST + + + +if NETWORKING + +config NET_L2_ETHERNET + default y + + + +endif # NETWORKING diff --git a/boards/phytium/ps2316_test/Kconfig.ps2316_test b/boards/phytium/ps2316_test/Kconfig.ps2316_test new file mode 100644 index 0000000000000000000000000000000000000000..73c32ecdcf06275c0bdd19e99dd456916651c9a1 --- /dev/null +++ b/boards/phytium/ps2316_test/Kconfig.ps2316_test @@ -0,0 +1,18 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config BOARD_PS2316_TEST + bool "phytium ps2316" + select SOC_PS2316 diff --git a/boards/phytium/ps2316_test/board.cmake b/boards/phytium/ps2316_test/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/phytium/ps2316_test/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/phytium/ps2316_test/board.yml b/boards/phytium/ps2316_test/board.yml new file mode 100644 index 0000000000000000000000000000000000000000..cfa4e482be7398f38dd53b823d55ee80b685625f --- /dev/null +++ b/boards/phytium/ps2316_test/board.yml @@ -0,0 +1,10 @@ +board: + name: ps2316_test + vendor: phytium + socs: + - name: ps2316 + variants: + - name: smp + - name: el2 + variants: + - name: smp diff --git a/boards/phytium/ps2316_test/ps2316_test.yaml b/boards/phytium/ps2316_test/ps2316_test.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e6fade4653a819f07a42258ff5b2ab0bb77f9e12 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test.yaml @@ -0,0 +1,10 @@ + +identifier: ps2316_test +name: Phytium ps2316 test +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/ps2316_test/ps2316_test_defconfig b/boards/phytium/ps2316_test/ps2316_test_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..23ad632a79648237f8da659bb690ce99d53c4962 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=8192 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_el2.yaml b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..19ec3faa26e84688ac409e2da9a20a3feee1e7ff --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2.yaml @@ -0,0 +1,7 @@ +identifier: ps2316_test/ps2316/el2 +name: Phytium ps2316 test +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_defconfig b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6a7fc9d29a198757581c36a1f5e8484f82d83f53 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_defconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp.yaml b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..074d7eae7da9605d7490a4014c8a222b9b075a40 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp.yaml @@ -0,0 +1,9 @@ +identifier: ps2316_test/ps2316/el2/smp +name: Phytium d2000 demo +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp_defconfig b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e066e47dbe5043d7b0dee65f91c55411797e08c3 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_el2_smp_defconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=8 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n + +# EL2 +CONFIG_USE_EL2=y diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_smp.yaml b/boards/phytium/ps2316_test/ps2316_test_ps2316_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..841a15cfb4e1c4731ef5d0916856d2f0dbf60f08 --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_smp.yaml @@ -0,0 +1,10 @@ + +identifier: ps2316_test/ps2316/smp +name: Phytium ps2316 test +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - smp diff --git a/boards/phytium/ps2316_test/ps2316_test_ps2316_smp_defconfig b/boards/phytium/ps2316_test/ps2316_test_ps2316_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..f4254033d811bc9cf66825c4df7d390be036967b --- /dev/null +++ b/boards/phytium/ps2316_test/ps2316_test_ps2316_smp_defconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_42=y +CONFIG_ARM64_PA_BITS_42=y +# Main stack size +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_ARMV8_A_NS=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#cache +CONFIG_CACHE_MANAGEMENT=y + +# Timer Drivers +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=12 +CONFIG_TIMEOUT_64BIT=y + +# CONFIG_SHELL=y +# CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n +# CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD=1 +# CONFIG_BOOT_BANNER=n diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index 8cb777c47699495937878310f88ce6f278bda799..18ce61c1a03f2dcbe74134fe7cfe6efec96f06c9 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -77,6 +77,10 @@ if("${ARCH}" STREQUAL "arm") endif() elseif(CONFIG_CPU_CORTEX_A9) set(GCC_M_CPU cortex-a9) + elseif(CONFIG_CPU_PHYTIUM_FT310) + set(GCC_M_CPU cortex-a9) + elseif(CONFIG_CPU_PHYTIUM_FT663) + set(GCC_M_CPU cortex-a9) else() message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined") endif() diff --git a/cmake/gcc-m-fpu.cmake b/cmake/gcc-m-fpu.cmake index a25cdf05679c8d32bfde9b95fb1d5e4ef5554a4f..163ff890c32a69705175792e3b657a9e57aa003f 100644 --- a/cmake/gcc-m-fpu.cmake +++ b/cmake/gcc-m-fpu.cmake @@ -23,6 +23,12 @@ if("${ARCH}" STREQUAL "arm") set(GCC_M_FPU fpv5-sp-d16) endif() endif() + elseif(CONFIG_CPU_CORTEX_A9) + if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) + set(GCC_M_FPU neon-fp-armv8) + elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION) + set(GCC_M_FPU fpv5-sp-d16) + endif() elseif(CONFIG_CPU_CORTEX_M) # Defines a mapping from GCC_M_CPU to FPU if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION) @@ -45,6 +51,12 @@ if("${ARCH}" STREQUAL "arm") set(FPU_FOR_cortex-m85+nodsp auto) set(GCC_M_FPU ${FPU_FOR_${GCC_M_CPU}}) + else() + if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) + set(GCC_M_FPU neon-fp-armv8) + elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION) + set(GCC_M_FPU fpv5-sp-d16) + endif() endif() endif() diff --git a/drivers/ethernet/CMakeLists.txt b/drivers/ethernet/CMakeLists.txt index 02b8f96bc9b181f8575c00466d24a755b9cd14ef..ea00379db1def3ea6aaa14ad9ab5710da07e07ad 100644 --- a/drivers/ethernet/CMakeLists.txt +++ b/drivers/ethernet/CMakeLists.txt @@ -40,6 +40,9 @@ zephyr_library_sources_ifdef(CONFIG_ETH_IVSHMEM eth_ivshmem.c eth_ivshmem_queue zephyr_library_sources_ifdef(CONFIG_ETH_ADIN2111 eth_adin2111.c) zephyr_library_sources_ifdef(CONFIG_ETH_LAN865X eth_lan865x.c oa_tc6.c) zephyr_library_sources_ifdef(CONFIG_ETH_XMC4XXX eth_xmc4xxx.c) +zephyr_library_sources_ifdef(CONFIG_ETH_PHYTIUM_XMAC eth_phytium_xmac.c) +zephyr_library_sources_ifdef(CONFIG_ETH_PHYTIUM_GMAC eth_phytium_gmac.c) +zephyr_library_sources_ifdef(CONFIG_ETH_PHYTIUM_XMAC_V2 eth_phytium_xmac_v2.c) if(CONFIG_ETH_NXP_S32_NETC) zephyr_library_sources(eth_nxp_s32_netc.c) diff --git a/drivers/ethernet/Kconfig b/drivers/ethernet/Kconfig index f54d659b7c038f7b18ecebc83fc03ad9f98c6f20..200a58d2c704cd8906148d2140548df093739b96 100644 --- a/drivers/ethernet/Kconfig +++ b/drivers/ethernet/Kconfig @@ -73,6 +73,9 @@ source "drivers/ethernet/Kconfig.adin2111" source "drivers/ethernet/Kconfig.numaker" source "drivers/ethernet/Kconfig.lan865x" source "drivers/ethernet/Kconfig.xmc4xxx" +source "drivers/ethernet/Kconfig.phytium_xmac" +source "drivers/ethernet/Kconfig.phytium_gmac" +source "drivers/ethernet/Kconfig.phytium_xmac_v2" source "drivers/ethernet/eth_nxp_enet_qos/Kconfig" diff --git a/drivers/ethernet/Kconfig.phytium_gmac b/drivers/ethernet/Kconfig.phytium_gmac new file mode 100644 index 0000000000000000000000000000000000000000..1743ea53f2b4f62dca5240282554850386354534 --- /dev/null +++ b/drivers/ethernet/Kconfig.phytium_gmac @@ -0,0 +1,22 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +menuconfig ETH_PHYTIUM_GMAC + bool "Phytium ETH_PHYTIUM_GMAC Ethernet driver" + default y + depends on DT_HAS_PHYTIUM_GMAC_ENABLED + help + Enable Phytium GMAC Ethernet driver. + diff --git a/drivers/ethernet/Kconfig.phytium_xmac b/drivers/ethernet/Kconfig.phytium_xmac new file mode 100644 index 0000000000000000000000000000000000000000..e9d527492105e9d6b7c86271a9a62f19cc299ad9 --- /dev/null +++ b/drivers/ethernet/Kconfig.phytium_xmac @@ -0,0 +1,22 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +menuconfig ETH_PHYTIUM_XMAC + bool "Phytium ETH_PHYTIUM_XMAC Ethernet driver" + default y + depends on DT_HAS_PHYTIUM_XMAC_ENABLED + help + Enable Phytium XMAC Ethernet driver. + diff --git a/drivers/ethernet/Kconfig.phytium_xmac_v2 b/drivers/ethernet/Kconfig.phytium_xmac_v2 new file mode 100644 index 0000000000000000000000000000000000000000..f3cc982f8bd19b4b792f206a78b5b838bf465fec --- /dev/null +++ b/drivers/ethernet/Kconfig.phytium_xmac_v2 @@ -0,0 +1,22 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +menuconfig ETH_PHYTIUM_XMAC_V2 + bool "Phytium ETH_PHYTIUM_XMAC_V2 Ethernet driver" + default y + depends on DT_HAS_PHYTIUM_XMAC_V2_ENABLED + help + Enable Phytium XMAC V2 Ethernet driver. + diff --git a/drivers/ethernet/eth_phytium_gmac.c b/drivers/ethernet/eth_phytium_gmac.c new file mode 100644 index 0000000000000000000000000000000000000000..5cbd3fc5c8382e2542bffa17c61e4cd4019b1d0a --- /dev/null +++ b/drivers/ethernet/eth_phytium_gmac.c @@ -0,0 +1,762 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fgmac.h" +#include "fgmac_hw.h" +#include "fgmac_phy.h" +#include "eth_phytium_gmac.h" + +#define LOG_MODULE_NAME phytium_gmac +#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL +#include +LOG_MODULE_REGISTER(LOG_MODULE_NAME); + +#define DT_DRV_COMPAT phytium_gmac + +#define GMAC_RX_DESCNUM 128 +#define GMAC_TX_DESCNUM 128 +#define FGMAC_DMA_MIN_ALIGN 128 +#define FGMAC_MAX_PACKET_SIZE 1600 +#define FGMAC_PHY_SPEED_10M 10 +#define FGMAC_PHY_SPEED_100M 100 +#define FGMAC_PHY_SPEED_1000M 1000 +#define FGMAC_PHY_HALF_DUPLEX 0 +#define FGMAC_PHY_FULL_DUPLEX 1 + +typedef void (*eth_phytium_gmac_config_irq_t)(const struct device *dev); + +#define FGMAC_CALL_EVT_HANDLER(instance_p, evt, dev) \ + {\ + if (NULL != (instance_p)->evt_handler[(evt)]) \ + { \ + (instance_p)->evt_handler[evt]((void *)(dev)); \ + }\ + } + +/* phy link */ +enum eth_phytium_link_speed { + /* The values of this enum are consecutively numbered */ + LINK_DOWN = 0, + LINK_10MBIT, + LINK_100MBIT, + LINK_1GBIT +}; + +struct eth_phytium_gmac_dev_cfg +{ + DEVICE_MMIO_ROM; + uint32_t instance_id; + eth_phytium_gmac_config_irq_t config_func; + uint32_t phy_poll_interval; + uint32_t autonegotiation; + uint32_t phy_speed; + uint32_t phy_duplex; + + uint8_t defer_rxp_to_queue; + uint8_t defer_txd_to_queue; +}; + +struct eth_phytium_gmac_dev_data +{ + DEVICE_MMIO_RAM; + struct net_if *iface; + FGmac instance; + enum eth_phytium_link_speed eff_link_speed; + + u8 tx_buf[GMAC_TX_DESCNUM * FGMAC_MAX_PACKET_SIZE] __aligned(FGMAC_DMA_MIN_ALIGN); + u8 rx_buf[GMAC_RX_DESCNUM * FGMAC_MAX_PACKET_SIZE] __aligned(FGMAC_DMA_MIN_ALIGN); + u8 tx_desc[GMAC_TX_DESCNUM * sizeof(FGmacDmaDesc)] __aligned(FGMAC_DMA_MIN_ALIGN); + u8 rx_desc[GMAC_RX_DESCNUM * sizeof(FGmacDmaDesc)] __aligned(FGMAC_DMA_MIN_ALIGN); + + uint8_t hwaddr[6]; + + struct k_work tx_done_work; + struct k_work rx_pend_work; + struct k_sem tx_done_sem; + + struct k_work_delayable phy_poll_delayed_work; + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + struct net_stats_eth stats; +#endif + + bool enable_jumbo : 1; + bool multicast_addr_filiter : 1; + bool started; +}; + +static void eth_phytium_gmac_tx_done_work(struct k_work *item); +static void eth_phytium_gmac_rx_pending_work(struct k_work *item); +static void eth_phytium_gmac_iface_init(struct net_if *iface); +static enum ethernet_hw_caps eth_phytium_gmac_get_capabilities(const struct device *dev); +static int eth_phytium_gmac_send(const struct device *dev, struct net_pkt *pkt); +static int eth_phytium_gmac_start_device(const struct device *dev); +static int eth_phytium_gmac_stop_device(const struct device *dev); +static void eth_phytium_gmac_isr(const struct device *dev); +#ifdef CONFIG_NET_STATISTICS_ETHERNET +static struct net_stats_eth *eth_phytium_gmac_stats(const struct device *dev); +#endif + +static const struct ethernet_api eth_phytium_gmac_apis = +{ + .iface_api.init = eth_phytium_gmac_iface_init, + .get_capabilities = eth_phytium_gmac_get_capabilities, + .send = eth_phytium_gmac_send, + .start = eth_phytium_gmac_start_device, + .stop = eth_phytium_gmac_stop_device, +#if defined(CONFIG_NET_STATISTICS_ETHERNET) + .get_stats = eth_phytium_gmac_stats, +#endif +}; + +static void eth_phytium_gmac_poll_phy(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct eth_phytium_gmac_dev_data *dev_data = CONTAINER_OF(dwork, struct eth_phytium_gmac_dev_data, phy_poll_delayed_work); + const struct device *dev = net_if_get_device(dev_data->iface); + const struct eth_phytium_gmac_dev_cfg *dev_conf = dev->config; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + uintptr base_addr = gmac_p->config.base_addr; + + u32 link_status = FGMAC_READ_REG32(base_addr, FGMAC_MAC_PHY_STATUS); + + if(FGMAC_RGSMIIIS_LNKSTS_UP == (FGMAC_RGSMIIIS_LNKSTS & link_status)) + { + switch(gmac_p->config.speed) + { + case FGMAC_PHY_SPEED_10M: + dev_data->eff_link_speed = LINK_10MBIT ; + break ; + case FGMAC_PHY_SPEED_100M: + dev_data->eff_link_speed = LINK_100MBIT ; + break ; + case FGMAC_PHY_SPEED_1000M: + dev_data->eff_link_speed = LINK_1GBIT ; + break ; + } + net_eth_carrier_on(dev_data->iface); + } + else + { + dev_data->eff_link_speed = LINK_DOWN; + net_eth_carrier_off(dev_data->iface); + + LOG_WRN("%s link down", dev->name); + } + + k_work_reschedule(&dev_data->phy_poll_delayed_work, K_MSEC(dev_conf->phy_poll_interval)); +} + +static void eth_phytium_gmac_iface_init(struct net_if *iface) +{ + const struct device *dev = net_if_get_device(iface); + struct eth_phytium_gmac_dev_data *dev_data = dev->data; + const struct eth_phytium_gmac_dev_cfg *dev_conf = dev->config; + + /* Register Ethernet MAC Address with the upper layer */ + dev_data->iface = iface; + net_if_set_link_addr(iface, dev_data->hwaddr, 6, NET_LINK_ETHERNET); + ethernet_init(iface); + net_if_carrier_off(iface); + + /* + * Initialize the (delayed) work items for RX pending, TX done + */ + k_work_init(&dev_data->tx_done_work, eth_phytium_gmac_tx_done_work); + k_work_init(&dev_data->rx_pend_work, eth_phytium_gmac_rx_pending_work); + k_work_init_delayable(&dev_data->phy_poll_delayed_work, + eth_phytium_gmac_poll_phy); + + /* Initialize TX completion semaphore */ + k_sem_init(&dev_data->tx_done_sem, 0, 1); + + dev_conf->config_func(dev); + /* Submit initial PHY status polling delayed work */ + + k_work_reschedule(&dev_data->phy_poll_delayed_work, K_NO_WAIT); +} + +static void eth_phytium_gmac_isr(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + uintptr base_addr = gmac_p->config.base_addr; + u32 status = 0; + + /* dma interrupt */ + status = FGMAC_READ_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET); + + if (FGMAC_DMA_STATUS_GLI & status) + { + FGMAC_CALL_EVT_HANDLER(gmac_p, FGMAC_PHY_STATUS_EVT, dev); + } + + if (FGMAC_DMA_STATUS_RI & status) + { + FGMAC_CALL_EVT_HANDLER(gmac_p, FGMAC_RX_COMPLETE_EVT, dev); + FGMAC_SET_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET, FGMAC_DMA_STATUS_RI); /* write to clear */ + } + + if (FGMAC_DMA_STATUS_TI & status) + { + FGMAC_CALL_EVT_HANDLER(gmac_p, FGMAC_TX_COMPLETE_EVT, dev); + FGMAC_SET_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET, FGMAC_DMA_STATUS_TI); /* write to clear */ + } + + if (FGMAC_DMA_STATUS_AIS & status) + { + FGMAC_CALL_EVT_HANDLER(gmac_p, FGMAC_DMA_ERR_EVT, dev); + FGMAC_SET_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET, FGMAC_DMA_STATUS_CLR_ABLE); + } + + FGMAC_WRITE_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET, status); /* write to clear */ + + /* RGMII/SGMII Interrupt */ + status = FGMAC_READ_REG32(base_addr, FGMAC_INTR_STATUS_OFFSET); + if (status & FGMAC_ISR_STATUS_RSIS) + { + /* status changed, read SGMII register to clear */ + FGMAC_READ_REG32(base_addr, FGMAC_MAC_PHY_STATUS); + } + + return; +} +static void EthLinkPhyStatusChecker(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + uintptr base_addr = gmac_p->config.base_addr; + u32 status = FGMAC_READ_REG32(base_addr, FGMAC_MAC_PHY_STATUS); + + if (FGMAC_RGSMIIIS_LNKSTS_UP == (FGMAC_RGSMIIIS_LNKSTS & status)) + { + LOG_INF("link is up\n"); + if(gmac_p->phy_link_status != FGMAC_LINKUP) + gmac_p->phy_link_status = FGMAC_NEGOTIATION; + } + else + { + LOG_INF("link is down\n"); + gmac_p->phy_link_status = FGMAC_LINKDOWN; + } + + return; +} + +static void EthLinkDmaErrChecker(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + uintptr base_addr = gmac_p->config.base_addr; + + u32 reg_val = FGMAC_READ_REG32(base_addr, FGMAC_DMA_INTR_OFFSET); + u32 status = FGMAC_READ_REG32(base_addr, FGMAC_DMA_STATUS_OFFSET); + + if ((FGMAC_DMA_STATUS_TPS & status) && (FGMAC_DMA_INTR_ENA_TSE & reg_val)) + { + LOG_ERR("Transmit process stopped"); + } + + if ((FGMAC_DMA_STATUS_TU & status) && (FGMAC_DMA_INTR_ENA_TUE & reg_val)) + { + LOG_ERR("Transmit Buffer Unavailable"); + } + + if ((FGMAC_DMA_STATUS_TJT & status) && (FGMAC_DMA_INTR_ENA_THE & reg_val)) + { + LOG_ERR("Transmit Jabber Timeout"); + } + + if ((FGMAC_DMA_STATUS_OVF & status) && (FGMAC_DMA_INTR_ENA_OVE & reg_val)) + { + LOG_ERR("Receive Overflow"); + } + + if ((FGMAC_DMA_STATUS_UNF & status) && (FGMAC_DMA_INTR_ENA_UNE & reg_val)) + { + LOG_ERR("Transmit Underflow"); + } + + if ((FGMAC_DMA_STATUS_RU & status) && (FGMAC_DMA_INTR_ENA_RUE & reg_val)) + { + LOG_ERR("Receive Buffer Unavailable"); + } + + if ((FGMAC_DMA_STATUS_RPS & status) && (FGMAC_DMA_INTR_ENA_RSE & reg_val)) + { + LOG_ERR("Receive Process Stopped"); + } + + if ((FGMAC_DMA_STATUS_RWT & status) && (FGMAC_DMA_INTR_ENA_RWE & reg_val)) + { + LOG_ERR("Receive Watchdog Timeout"); + } + + if ((FGMAC_DMA_STATUS_ETI & status) && (FGMAC_DMA_INTR_ENA_ETE & reg_val)) + { + LOG_ERR("Early Transmit Interrupt"); + } + + if ((FGMAC_DMA_STATUS_FBI & status) && (FGMAC_DMA_INTR_ENA_FBE & reg_val)) + { + LOG_ERR("Fatal Bus Error"); + } + + return; +} + +static void EthLinkStatusChecker(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + uintptr base_addr = gmac_p->config.base_addr; + u32 status = FGMAC_READ_REG32(base_addr, FGMAC_MAC_PHY_STATUS); + u32 speed_status, duplex_status; + u32 speed, duplex; + + /* Check the link status */ + if (FGMAC_RGSMIIIS_LNKSTS_UP == (FGMAC_RGSMIIIS_LNKSTS & status)) + { + speed_status = FGMAC_RGSMIIIS_SPEED & status; + duplex_status = FGMAC_RGSMIIIS_LNKMODE & status; + + if (FGMAC_RGSMIIIS_SPEED_125MHZ == speed_status) + speed = FGMAC_PHY_SPEED_1000; + else if (FGMAC_RGSMIIIS_SPEED_25MHZ == speed_status) + speed = FGMAC_PHY_SPEED_100; + else + speed = FGMAC_PHY_SPEED_10; + + if (FGMAC_RGSMIIIS_LNKMODE_HALF == duplex_status) + duplex = FGMAC_PHY_MODE_HALFDUPLEX; + else + duplex = FGMAC_PHY_MODE_FULLDUPLEX; + + LOG_INF("link is up --- %d/%s", + speed, (FGMAC_PHY_MODE_FULLDUPLEX == duplex) ? "full" : "half"); + } + else + { + LOG_INF("link is down ---"); + } +} + +static void eth_phytium_gmac_handle_tx_done(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + FGmacResumeDmaSend(gmac_p->config.base_addr); + LOG_INF("resume trans"); + + k_sem_give(&dev_data->tx_done_sem); + return; +} + +static void eth_phytium_gmac_tx_done_work(struct k_work *item) +{ + struct eth_phytium_gmac_dev_data *dev_data = CONTAINER_OF(item, struct eth_phytium_gmac_dev_data, tx_done_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_gmac_handle_tx_done(dev); +} + +static void FGmacTxDoneHandler(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + struct eth_phytium_gmac_dev_cfg *dev_conf = (struct eth_phytium_gmac_dev_cfg *)dev->config; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + if (dev_conf->defer_txd_to_queue) + { + k_work_submit(&dev_data->tx_done_work); + } + else + { + eth_phytium_gmac_handle_tx_done(dev); + } +} + +static void eth_phytium_gmac_handle_rx_pending(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + struct net_pkt *pkt; + volatile FGmacDmaDesc *dma_rx_desc; + u16 rx_data_length = 0; + u8 *buffer; + + u32 desc_buffer_index; /* For Current Desc buffer buf position */ + u32 desc_buffer_last_index;/* For Last Desc buffer buf position */ + u32 rx_buffer_size = FGMAC_MAX_PACKET_SIZE & GENMASK(10, 0); /* Size of a rx buffer */ + + /* get received frame */ + if (FGmacRecvFrame(gmac_p) != FT_SUCCESS) + { + LOG_ERR("FGmacRecvFrame failed!\n"); + } + + desc_buffer_last_index = gmac_p->rx_ring.desc_buf_idx; + rx_data_length = (gmac_p->rx_desc[desc_buffer_last_index].status & FGMAC_DMA_RDES0_FRAME_LEN_MASK) >> FGMAC_DMA_RDES0_FRAME_LEN_SHIFT; + buffer = (u8 *)(intptr)(gmac_p->rx_desc[gmac_p->rx_ring.desc_first_buf_idx].buf_addr); + + pkt = net_pkt_rx_alloc_with_buffer(dev_data->iface, rx_data_length, AF_UNSPEC, 0, K_FOREVER); + if (pkt == NULL) + { + LOG_ERR("RX packet buffer alloc failed: %u bytes", rx_data_length); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.errors.rx++; + dev_data->stats.error_details.rx_no_buffer_count++; +#endif + } + else + { + desc_buffer_index = gmac_p->rx_ring.desc_first_buf_idx; + while (rx_data_length > rx_buffer_size) + { + net_pkt_write(pkt, buffer, rx_buffer_size); + rx_data_length = rx_data_length - rx_buffer_size; + FGMAC_DMA_INC_DESC(desc_buffer_index, gmac_p->rx_ring.desc_max_num); + dma_rx_desc = &gmac_p->rx_desc[desc_buffer_index]; + buffer = (u8 *)(intptr)(dma_rx_desc->buf_addr); + } + desc_buffer_index = gmac_p->rx_ring.desc_first_buf_idx; + dma_rx_desc = &gmac_p->rx_desc[desc_buffer_index]; + net_pkt_write(pkt, buffer, rx_data_length); + if (net_recv_data(dev_data->iface, pkt) < 0) + { + LOG_ERR("%s RX packet hand-over to IP stack failed", dev->name); + net_pkt_unref(pkt); + } + } + + for (desc_buffer_index = gmac_p->rx_ring.desc_first_buf_idx; desc_buffer_index != gmac_p->rx_ring.desc_idx; FGMAC_DMA_INC_DESC(desc_buffer_index, gmac_p->rx_ring.desc_max_num)) + { + dma_rx_desc = &gmac_p->rx_desc[desc_buffer_index]; + dma_rx_desc->status |= FGMAC_DMA_RDES0_OWN; + } + /* Sync index */ + gmac_p->rx_ring.desc_buf_idx = gmac_p->rx_ring.desc_idx; + + FGmacResumeDmaRecv(gmac_p->config.base_addr); +} + +static void eth_phytium_gmac_rx_pending_work(struct k_work *item) +{ + struct eth_phytium_gmac_dev_data *dev_data = CONTAINER_OF(item, struct eth_phytium_gmac_dev_data, rx_pend_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_gmac_handle_rx_pending(dev); +} + +static void FGmacRecvHandler(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + struct eth_phytium_gmac_dev_cfg *dev_conf = (struct eth_phytium_gmac_dev_cfg *)dev->config; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + if (dev_conf->defer_rxp_to_queue) + { + k_work_submit(&dev_data->rx_pend_work); + } + else + { + LOG_INF("recv data \r\n"); + eth_phytium_gmac_handle_rx_pending(dev); + LOG_INF("recv data exit \r\n"); + } +} + +static int FGmacSetupIsr(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + /* disable all gmac & dma intr */ + FGmacSetInterruptMask(gmac_p, FGMAC_CTRL_INTR, FGMAC_ISR_MASK_ALL_BITS); + FGmacSetInterruptMask(gmac_p, FGMAC_DMA_INTR, FGMAC_DMA_INTR_ENA_ALL_MASK); + + FGmacRegisterEvtHandler(gmac_p, FGMAC_PHY_STATUS_EVT, EthLinkPhyStatusChecker); + FGmacRegisterEvtHandler(gmac_p, FGMAC_DMA_ERR_EVT, EthLinkDmaErrChecker); + FGmacRegisterEvtHandler(gmac_p, FGMAC_LINK_STATUS_EVT, EthLinkStatusChecker); + + FGmacRegisterEvtHandler(gmac_p, FGMAC_TX_COMPLETE_EVT, FGmacTxDoneHandler); + FGmacRegisterEvtHandler(gmac_p, FGMAC_RX_COMPLETE_EVT, FGmacRecvHandler); + + return 0; +} + +static int eth_phytium_gmac_dev_init(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + struct eth_phytium_gmac_dev_cfg *dev_conf = (struct eth_phytium_gmac_dev_cfg *)dev->config; + FGmac *gmac_p; + FError status; + FGmacConfig mac_config; + gmac_p = &dev_data->instance; + mac_config = *FGmacLookupConfig(dev_conf->instance_id); + /* init base */ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + /* config init */ + mac_config.base_addr = DEVICE_MMIO_GET(dev); + mac_config.instance_id = 0; + + if(dev_conf->autonegotiation) + { + mac_config.en_auto_negtiation = 1; + } + else + { + mac_config.en_auto_negtiation = 0; + } + + switch (dev_conf->phy_speed) + { + case FGMAC_PHY_SPEED_10M: + mac_config.speed = 10; + break; + case FGMAC_PHY_SPEED_100M: + mac_config.speed = 100; + break; + case FGMAC_PHY_SPEED_1000M: + mac_config.speed = 1000; + break; + default: + LOG_ERR("setting speed is not valid , speed is %d", dev_conf->phy_speed); + return -EIO; + } + + switch(dev_conf->phy_duplex) + { + case FGMAC_PHY_HALF_DUPLEX: + mac_config.duplex_mode = 0; + break; + case FGMAC_PHY_FULL_DUPLEX: + mac_config.duplex_mode = 1; + break; + } + status = FGmacCfgInitialize(gmac_p, &mac_config); + + if (status != FGMAC_SUCCESS) + { + LOG_ERR("In %s:EmacPs Configuration Failed....\r\n", __func__); + } + if(dev_data->multicast_addr_filiter) + { + FGmacMulticastHashEnable(gmac_p); + } + + if(dev_data->enable_jumbo) + { + FGmacJumboEnable(gmac_p); + } + + FGmacSetMacAddr(dev_data->instance.config.base_addr, (void *)(dev_data->hwaddr)); + /* step 4: initialize phy */ + status = FGmacPhyCfgInitialize(gmac_p, GMAC_PHY_RESET_ENABLE); + if(status!=FGMAC_SUCCESS) + { + LOG_ERR("FGmacPhyCfgInitialize: init phy failed \r\n"); + } + /* step 5: initialize dma */ + /* Initialize Rx Description list : ring Mode */ + status = FGmacSetupRxDescRing(gmac_p, (FGmacDmaDesc *)(dev_data->rx_desc), dev_data->rx_buf, FGMAC_MAX_PACKET_SIZE, GMAC_RX_DESCNUM); + if (FT_SUCCESS != status) + { + LOG_ERR("gmac setup rx return err code %d\r\n", status); + FASSERT(FT_SUCCESS == status); + } + + /* Initialize Tx Description list : ring Mode */ + status = FGmacSetupTxDescRing(gmac_p, (FGmacDmaDesc *)(dev_data->tx_desc), dev_data->tx_buf, FGMAC_MAX_PACKET_SIZE, GMAC_TX_DESCNUM); + if (FT_SUCCESS != status) + { + LOG_ERR("gmac setup tx return err code %d\r\n", status); + FASSERT(FT_SUCCESS == status); + } + + /* initialize interrupt */ + FGmacSetupIsr(dev); + return 0; +} + +static int eth_phytium_gmac_start_device(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + /* Setup callbacks */ + if (dev_data->started) { + return 0; + } + dev_data->started = true; + + FGmac *gmac_p; + gmac_p = &dev_data->instance; + FGmacStartTrans(gmac_p); + + FGmacSetInterruptUmask(gmac_p, FGMAC_CTRL_INTR, FGMAC_ISR_MASK_RSIM); + FGmacSetInterruptUmask(gmac_p, FGMAC_DMA_INTR, FGMAC_DMA_INTR_ENA_NIE | FGMAC_DMA_INTR_ENA_RIE | FGMAC_DMA_INTR_ENA_AIE | FGMAC_DMA_INTR_ENA_TIE); + return 0; +} + +static int eth_phytium_gmac_stop_device(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + /* Setup callbacks */ + if (dev_data->started) { + return 0; + } + dev_data->started = false; + + FGmac *gmac_p; + gmac_p = &dev_data->instance; + + /* Cancel the delayed work that polls the link state */ + if (k_work_delayable_remaining_get(&dev_data->phy_poll_delayed_work) != 0) + { + k_work_cancel_delayable(&dev_data->phy_poll_delayed_work); + } + + FGmacStopTrans(gmac_p); + return 0; +} + +static enum ethernet_hw_caps eth_phytium_gmac_get_capabilities(const struct device *dev) +{ + struct eth_phytium_gmac_dev_cfg *dev_cfg = (struct eth_phytium_gmac_dev_cfg *)dev->config; + enum ethernet_hw_caps caps = (enum ethernet_hw_caps)0; + switch (dev_cfg->phy_speed) + { + case FGMAC_PHY_SPEED_10M: + caps |= ETHERNET_LINK_10BASE_T; + break; + case FGMAC_PHY_SPEED_100M: + caps |= (ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + case FGMAC_PHY_SPEED_1000M: + caps |= (ETHERNET_LINK_1000BASE_T | + ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + } + + return caps; +} +static int eth_phytium_gmac_send(const struct device *dev, struct net_pkt *pkt) +{ + struct eth_phytium_gmac_dev_data *dev_data = (struct eth_phytium_gmac_dev_data *)dev->data; + int res; + FError ret; + FGmac *gmac_p; + volatile FGmacDmaDesc *dma_tx_desc; + u8 *buffer = NULL; + gmac_p = &dev_data->instance; + dma_tx_desc = &gmac_p->tx_desc[gmac_p->tx_ring.desc_buf_idx]; + buffer = (u8 *)(intptr)(dma_tx_desc->buf_addr); + + if (buffer == NULL) + { + LOG_ERR(" error buffer is 0 \r\n"); + return -EIO; + } + + if (!dev_data->started || (!net_if_flag_is_set(dev_data->iface, NET_IF_UP))) + { +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + return -EIO; + } + + uint16_t remaining_read = net_pkt_get_len(pkt); + uint16_t total_len = remaining_read; + if (total_len == 0) { + LOG_ERR("%s cannot TX, zero packet length", dev->name); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + return -EINVAL; + } + + while (remaining_read > FGMAC_MAX_PACKET_SIZE) + { + if (net_pkt_read(pkt, buffer, FGMAC_MAX_PACKET_SIZE)) { + res = -ENOBUFS; + goto error; + } + FGMAC_DMA_INC_DESC(gmac_p->tx_ring.desc_buf_idx, gmac_p->tx_ring.desc_max_num); + dma_tx_desc = &gmac_p->tx_desc[gmac_p->tx_ring.desc_buf_idx]; + buffer = (u8 *)(intptr)(dma_tx_desc->buf_addr); + remaining_read -= FGMAC_MAX_PACKET_SIZE; + } + if (net_pkt_read(pkt, buffer, remaining_read)) + { + res = -ENOBUFS; + goto error; + } + else + { + } + + FGMAC_DMA_INC_DESC(gmac_p->tx_ring.desc_buf_idx, gmac_p->tx_ring.desc_max_num); + + ret = FGmacSendFrame(gmac_p, total_len); + if (ret != FGMAC_SUCCESS) + { + res = -ENOBUFS; + LOG_INF("error errval = ERR_USE; FGmacSendFrame\r\n"); + goto error; + } + +error: + FGmacResmuDmaUnderflow(gmac_p->config.base_addr); + + return res; +} + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + +static struct net_stats_eth *eth_phytium_gmac_stats(const struct device *dev) +{ + struct eth_phytium_gmac_dev_data *dev_data = dev->data; + + return &dev_data->stats; +} +#endif + +DT_INST_FOREACH_STATUS_OKAY(ETH_PHYTIUM_GMAC_INITIALIZE) \ No newline at end of file diff --git a/drivers/ethernet/eth_phytium_gmac.h b/drivers/ethernet/eth_phytium_gmac.h new file mode 100644 index 0000000000000000000000000000000000000000..e821b9623ce43bec9e98229b4f999ffff8f8fbdd --- /dev/null +++ b/drivers/ethernet/eth_phytium_gmac.h @@ -0,0 +1,51 @@ +#ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_GMAC_H_ +#define _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_GMAC_H_ + +/* Device configuration data declaration macro */ +#define ETH_PHYTIUM_GMAC_DEV_CONFIG(port) \ +static const struct eth_phytium_gmac_dev_cfg eth_phytium_gmac##port##_dev_cfg = {\ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)), \ + .instance_id = port, \ + .config_func = eth_phytium_gmac##port##_irq_config,\ + .phy_poll_interval = DT_INST_PROP(port, phy_poll_interval),\ + .defer_rxp_to_queue = !DT_INST_PROP(port, handle_rx_in_isr),\ + .defer_txd_to_queue = DT_INST_PROP(port, handle_tx_in_workq),\ + .autonegotiation = (uint32_t)DT_INST_PROP(port, autonegotiation),\ + .phy_speed = (uint32_t)DT_INST_PROP(port, phy_speed),\ + .phy_duplex = (uint32_t)DT_INST_PROP(port, phy_duplex),\ +}; + +/* Device run-time data declaration macro */ +#define ETH_PHYTIUM_GMAC_DEV_DATA(port) \ +static struct eth_phytium_gmac_dev_data eth_phytium_gmac##port##_dev_data = {\ + .hwaddr = DT_INST_PROP(port, local_mac_address),\ +}; + +/* Interrupt configuration function macro */ +#define ETH_PHYTIUM_GMAC_CONFIG_IRQ_FUNC(port) \ +static void eth_phytium_gmac##port##_irq_config(const struct device *dev)\ +{\ + ARG_UNUSED(dev);\ + IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority),\ + eth_phytium_gmac_isr, DEVICE_DT_INST_GET(port), 0);\ + irq_enable(DT_INST_IRQN(port));\ +} + +#define ETH_PHYTIUM_GMAC_NET_DEV_INIT(port) \ +ETH_NET_DEVICE_DT_INST_DEFINE(port,\ + eth_phytium_gmac_dev_init,\ + NULL,\ + ð_phytium_gmac##port##_dev_data,\ + ð_phytium_gmac##port##_dev_cfg,\ + CONFIG_ETH_INIT_PRIORITY,\ + ð_phytium_gmac_apis,\ + NET_ETH_MTU); + +/* Top-level device initialization macro - bundles all of the above */ +#define ETH_PHYTIUM_GMAC_INITIALIZE(port) \ +ETH_PHYTIUM_GMAC_CONFIG_IRQ_FUNC(port);\ +ETH_PHYTIUM_GMAC_DEV_CONFIG(port);\ +ETH_PHYTIUM_GMAC_DEV_DATA(port);\ +ETH_PHYTIUM_GMAC_NET_DEV_INIT(port);\ + +#endif diff --git a/drivers/ethernet/eth_phytium_xmac.c b/drivers/ethernet/eth_phytium_xmac.c new file mode 100644 index 0000000000000000000000000000000000000000..ac697423b8fd21801daaf43a0194f79bda12fdf8 --- /dev/null +++ b/drivers/ethernet/eth_phytium_xmac.c @@ -0,0 +1,1487 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +#include "fparameters.h" +#include "fxmac.h" +#include "fxmac_hw.h" +#include "fxmac_bdring.h" +#include "fxmac_phy.h" +#include "eth_ieee_reg.h" +#include "eth_phytium_xmac.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + + +#define LOG_MODULE_NAME phytium_xmac +#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL +#include +LOG_MODULE_REGISTER(LOG_MODULE_NAME); + +#define DT_DRV_COMPAT phytium_xmac + + +/* dma buffer */ +#define ETH_PHYTIUM_BDL_ALIGNMENT 256 +#define ETH_PHYTIUM_BUFFER_ALIGNMENT ETH_PHYTIUM_BDL_ALIGNMENT +#define ETH_ALIGNMENT_OFFSET_DEFINED(buffer_size) ((buffer_size\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1)) + + +/* IRQ handler function type */ +typedef void (*eth_phytiium_xmac_config_irq_t)(const struct device *dev); + +typedef enum +{ + FXMAC_LWIP_PORT_INTERFACE_SGMII = 0, + FXMAC_LWIP_PORT_INTERFACE_RMII, + FXMAC_LWIP_PORT_INTERFACE_RGMII, + FXMAC_LWIP_PORT_INTERFACE_USXGMII, + FXMAC_LWIP_PORT_INTERFACE_LENGTH +} FXmacLwipPortInterface; + + +#define FXMAC_PHY_SPEED_10M 10 +#define FXMAC_PHY_SPEED_100M 100 +#define FXMAC_PHY_SPEED_1000M 1000 +#define FXMAC_PHY_SPEED_10G 10000 + + +/* phy link */ +enum eth_phytium_link_speed { + /* The values of this enum are consecutively numbered */ + LINK_DOWN = 0, + LINK_10MBIT, + LINK_100MBIT, + LINK_1GBIT +}; + +#define FXMAC_BD_TO_INDEX(ringptr, bdptr) \ + (((uintptr)bdptr - (uintptr)(ringptr)->base_bd_addr) / (ringptr)->separation) + +struct eth_phytium_xmac_dev_cfg { + DEVICE_MMIO_ROM; + uint32_t instance_id; /* */ + eth_phytiium_xmac_config_irq_t config_func; + uint32_t pll_clock_frequency; + + uint32_t phy_poll_interval; + uint8_t defer_rxp_to_queue; + uint8_t defer_txd_to_queue; + + uint8_t rxbd_count; /* rx bdl count */ + uint8_t txbd_count; /* tx bdl count */ + uint16_t rx_buffer_size; /* per buffer size */ + uint16_t tx_buffer_size; + + /* dtc defined */ + uint32_t phy_speed; /* FXMAC_PHY_SPEED_XX */ + uint32_t interface_mode; /* followed by FXmacLwipPortInterface */ + uint32_t dma_brust_length; + uint32_t max_queue_num; /* Number of Xmac Controller Queues */ + bool phy_autonegotiation : 1; + bool enable_fdx : 1; + bool enable_jumbo : 1; + bool enable_ucast_hash :1; + bool copy_all_frames :1; + bool disable_reject_fcs_crc_errors:1; + bool enable_mcast_hash :1; + +}; + + +struct eth_phytium_xmac_dev_data { + DEVICE_MMIO_RAM; /* used for controller base address */ + struct net_if *iface; + FXmac instance; + uint8_t mac_addr[6]; + enum eth_phytium_link_speed eff_link_speed; + struct k_work tx_done_work; + struct k_work rx_pend_work; + struct k_sem tx_done_sem; + + struct k_sem ring_sem; + + uint8_t phy_addr; + uint32_t phy_id; + struct k_work_delayable phy_poll_delayed_work; + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + struct net_stats_eth stats; +#endif + + uint8_t *rx_bdspace; + uint8_t *rx_bdspace_virt; + uint8_t *tx_bdspace; + uint8_t *tx_bdspace_virt; + + uint8_t *first_rx_buffer; + uint8_t *first_rx_buffer_virt; + uint8_t *first_tx_buffer; + uint8_t *first_tx_buffer_virt; + + bool started; +}; + + +static int eth_phytium_xmac_dev_init(const struct device *dev); +static void eth_phytium_xmac_iface_init(struct net_if *iface); +static enum ethernet_hw_caps eth_phytium_xmac_get_capabilities(const struct device *dev); +static int eth_phytium_xmac_send(const struct device *dev, struct net_pkt *pkt); +static int eth_phytium_xmac_start_device(const struct device *dev); +static int eth_phytium_xmac_stop_device(const struct device *dev); +#ifdef CONFIG_NET_STATISTICS_ETHERNET +static struct net_stats_eth *eth_phytium_xmac_stats(const struct device *dev); +#endif + +static void eth_phytium_xmac_isr(const struct device *dev); + +static const struct ethernet_api eth_phytium_xmac_apis = { + .iface_api.init = eth_phytium_xmac_iface_init, + .get_capabilities = eth_phytium_xmac_get_capabilities, + .send = eth_phytium_xmac_send, + .start = eth_phytium_xmac_start_device, + .stop = eth_phytium_xmac_stop_device, +#if defined(CONFIG_NET_STATISTICS_ETHERNET) + .get_stats = eth_phytium_xmac_stats, +#endif +}; + + +/* + * Insert the configuration & run-time data for all GEM instances which + * are enabled in the device tree of the current target board. + */ +DT_INST_FOREACH_STATUS_OKAY(ETH_PHYTIUM_XMAC_INITIALIZE) + + +static void FXmacSetupIsr(const struct device *dev); + +static uint32_t phy_autoneg_status(FXmac *xmac_p, uint32_t phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + FXmacPhyRead(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET, &status); + + if (status & PHY_STATUS_AUTONEGOTIATE_COMPLETE) + return 1; + return 0; +} + +/** + * @name: phy_link_detect + * @msg: Get current link status + * @note: + * @param {FXmac} *fxmac_p + * @param {u32} phy_addr + * @return {*} 1 is link up , 0 is link down + */ +static u32 phy_link_detect(FXmac *xmac_p, u32 phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + + FXmacPhyRead(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET, &status); + + if (status & PHY_STAT_LINK_STATUS) + return 1; + return 0; +} + +FXmacLinkStatus FXmacRgmiiLinkDetect(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + instance_p = &dev_data->instance; + + u32 phy_link_status; + + + phy_link_status = phy_link_detect(instance_p, instance_p->phy_address); + + if ((instance_p->link_status == FXMAC_LINKUP) && (!phy_link_status)) + instance_p->link_status = FXMAC_LINKDOWN; + + switch (instance_p->link_status) + { + case FXMAC_LINKUP: + return FXMAC_LINKUP; + case FXMAC_LINKDOWN: + instance_p->link_status = FXMAC_NEGOTIATING; + LOG_DBG("Ethernet Link down"); + return FXMAC_LINKDOWN; + case FXMAC_NEGOTIATING: + if ((phy_link_status == FXMAC_LINKUP) && phy_autoneg_status(instance_p, instance_p->phy_address)) + { + if(FXmacPhyInit(instance_p, instance_p->config.speed, instance_p->config.duplex, instance_p->config.auto_neg, XMAC_PHY_RESET_DISABLE)) + { + return FXMAC_LINKDOWN; + } + + FXmacSelectClk(instance_p); + FXmacInitInterface(instance_p); + + /* Initiate Phy setup to get link speed */ + instance_p->link_status = FXMAC_LINKUP; + LOG_DBG("Ethernet Link up"); + return FXMAC_LINKUP; + } + return FXMAC_LINKDOWN; + default: + return FXMAC_LINKDOWN; + } +} + +FXmacLinkStatus FXmacSgmiiLinkDetect(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + u32 ctrl; + u32 link, link_status; + instance_p = &dev_data->instance; + + ctrl = FXMAC_READREG32(instance_p->config.base_address, FXMAC_PCS_AN_LP_OFFSET); + link = (ctrl & FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_STATUS) >> FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_OFFSET; + + switch (link) + { + case 0: + link_status = FXMAC_LINKDOWN; + break; + case 1: + link_status = FXMAC_LINKUP; + break; + default: + LOG_ERR("link status is error 0x%x \r\n", link); + return FXMAC_LINKDOWN; + } + + if (link_status == FXMAC_LINKUP) + { + if (link_status != instance_p->link_status) + { + instance_p->link_status = FXMAC_NEGOTIATING; + LOG_INF("need NEGOTIATING"); + } + } + else + { + instance_p->link_status = FXMAC_LINKDOWN; + } + + if (instance_p->link_status == FXMAC_NEGOTIATING) + { + /* renegotiate */ + if (FXmacPhyInit(instance_p, instance_p->config.speed, instance_p->config.duplex, instance_p->config.auto_neg,XMAC_PHY_RESET_DISABLE)) + { + LOG_ERR("FXmacPhyInit is error \r\n"); + return FXMAC_LINKDOWN; + } + else + { + FXmacSelectClk(instance_p); + FXmacInitInterface(instance_p); + instance_p->link_status = FXMAC_LINKUP; + return FXMAC_LINKUP; + } + } + return instance_p->link_status; +} + +static void eth_phytium_xmac_poll_phy(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct eth_phytium_xmac_dev_data *dev_data = CONTAINER_OF(dwork, + struct eth_phytium_xmac_dev_data, phy_poll_delayed_work); + const struct device *dev = net_if_get_device(dev_data->iface); + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + FXmacLinkStatus link_status = FXMAC_LINKDOWN; + FXmac *instance_p; + instance_p = &dev_data->instance; + + if(instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII) + { + link_status = FXmacSgmiiLinkDetect(dev); + } + else if((instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RMII) || (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RGMII)) + { + link_status = FXmacRgmiiLinkDetect(dev); + } + + if(link_status == FXMAC_LINKDOWN) + { + dev_data->eff_link_speed = LINK_DOWN; + net_eth_carrier_off(dev_data->iface); + + LOG_WRN("%s link down", dev->name); + } + else if(link_status == FXMAC_LINKUP) + { + switch(instance_p->config.speed) + { + case FXMAC_SPEED_10: + dev_data->eff_link_speed = LINK_10MBIT; + break; + case FXMAC_SPEED_100: + dev_data->eff_link_speed = LINK_100MBIT; + break; + case FXMAC_SPEED_1000: + dev_data->eff_link_speed = LINK_1GBIT; + break; + } + net_eth_carrier_on(dev_data->iface); + } + + k_work_reschedule(&dev_data->phy_poll_delayed_work, + K_MSEC(dev_conf->phy_poll_interval)); + +} + +/** + * @name: eth_phytium_xmac_get_capabilities + * @msg: Reports the hardware capabilities of the Ethernet device, such as supported speeds and duplex modes. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {enum ethernet_hw_caps} A bitmask of supported features defined in `enum ethernet_hw_caps`. + */ +static enum ethernet_hw_caps eth_phytium_xmac_get_capabilities(const struct device *dev) +{ + struct eth_phytium_xmac_dev_cfg *dev_cfg = (struct eth_phytium_xmac_dev_cfg *)dev->config; + enum ethernet_hw_caps caps = (enum ethernet_hw_caps)0; + + switch (dev_cfg->phy_speed) + { + case FXMAC_PHY_SPEED_10M: + caps |= ETHERNET_LINK_10BASE_T; + break; + case FXMAC_PHY_SPEED_100M: + caps |= (ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + case FXMAC_PHY_SPEED_1000M: + caps |= (ETHERNET_LINK_1000BASE_T | + ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + case FXMAC_PHY_SPEED_10G: + caps |= (ETHERNET_LINK_1000BASE_T | + ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + } + + if (dev_cfg->enable_fdx) { + caps |= ETHERNET_DUPLEX_SET; + } + + if (dev_cfg->copy_all_frames) { + caps |= ETHERNET_PROMISC_MODE; + } + return caps; +} + +static int eth_phytium_xmac_config_convert(struct eth_phytium_xmac_dev_cfg *dev_conf,FXmacConfig *mac_config,uint32_t *options) +{ + *options = 0; + switch (dev_conf->interface_mode) + { + case FXMAC_LWIP_PORT_INTERFACE_SGMII: + mac_config->interface = FXMAC_PHY_INTERFACE_MODE_SGMII; + LOG_INF("SGMII select"); + break; + case FXMAC_LWIP_PORT_INTERFACE_RMII: + mac_config->interface = FXMAC_PHY_INTERFACE_MODE_RMII; + LOG_INF("RMII select"); + break; + case FXMAC_LWIP_PORT_INTERFACE_RGMII: + LOG_INF("RGMII select"); + mac_config->interface = FXMAC_PHY_INTERFACE_MODE_RGMII; + break; + case FXMAC_LWIP_PORT_INTERFACE_USXGMII: + LOG_INF("USXGMII select"); + mac_config->interface = FXMAC_PHY_INTERFACE_MODE_USXGMII; + break; + default: + return -EINVAL; + } + + switch (dev_conf->phy_speed) + { + case FXMAC_PHY_SPEED_10M: + mac_config->speed = FXMAC_SPEED_10; + break; + case FXMAC_PHY_SPEED_100M: + mac_config->speed = FXMAC_SPEED_100; + break; + case FXMAC_PHY_SPEED_1000M: + mac_config->speed = FXMAC_SPEED_1000; + break; + case FXMAC_PHY_SPEED_10G: + LOG_INF("select FXMAC_PHY_SPEED_10G"); + mac_config->speed = FXMAC_SPEED_10000; + break; + default: + return -EINVAL; + } + + mac_config->duplex = dev_conf->enable_fdx? 1:0; /* 1 is full-duplex , 0 is half-duplex */ + mac_config->auto_neg = dev_conf->phy_autonegotiation; /* Enable auto-negotiation - when set active high, + autonegotiation operation is enabled. */ + mac_config->pclk_hz = dev_conf->pll_clock_frequency; + mac_config->max_queue_num = dev_conf->max_queue_num; /* Number of Xmac Controller Queues */ + mac_config->tx_queue_id = 0; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */ + mac_config->rx_queue_id = 0; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */ + mac_config->dma_brust_length = dev_conf->dma_brust_length; /* burst length */ + mac_config->network_default_config = FXMAC_DEFAULT_OPTIONS; +#if defined(FXMAC_CAPS) + mac_config->caps = FXMAC_CAPS; /* used to configure tail ptr feature */ +#else + mac_config->caps = 0; +#endif + + /* options */ + if(dev_conf->enable_jumbo) + { + *options |= FXMAC_JUMBO_ENABLE_OPTION; + } + + if(dev_conf->enable_ucast_hash) + { + *options |= FXMAC_UNICAST_OPTION; + } + + if(dev_conf->enable_mcast_hash) + { + *options |= FXMAC_MULTICAST_OPTION; + } + + if(dev_conf->copy_all_frames) + { + *options |= FXMAC_PROMISC_OPTION; + } + + if(dev_conf->disable_reject_fcs_crc_errors) + { + *options |= FXMAC_FCS_STRIP_OPTION; + } + + if(mac_config->caps & FXMAC_CAPS_TAILPTR) + { + *options |= FXMAC_TAIL_PTR_OPTION; + } + + return 0; +} + +/* irq init */ +static int eth_phytium_xmac_setuphandler(const struct device *dev) +{ + + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + + FXmacBd bdtemplate; + FXmacBdRing *rxringptr, *txringptr; + FXmacBd *rxbd; + int i; + u32 bdindex; + u32 *temp; + instance_p = &dev_data->instance; + /* init buffer to data */ + /* Initial configuration of the RX/TX BD rings */ + DT_INST_FOREACH_STATUS_OKAY(ETH_PHYTIUM_XMAC_INIT_BD_RING) + rxringptr = &FXMAC_GET_RXRING((*instance_p)); + txringptr = &FXMAC_GET_TXRING((*instance_p)); + + /* Setup RxBD space. */ + FXMAC_BD_CLEAR(&bdtemplate); + + /* Create the RxBD ring */ + if(FXmacBdRingCreate(rxringptr, (uintptr)dev_data->rx_bdspace, + (uintptr)dev_data->rx_bdspace, + ETH_PHYTIUM_BDL_ALIGNMENT, + dev_conf->rxbd_count)) + { + LOG_ERR("Error setting up RxBD space\r\n"); + return -EIO; + } + + if(FXmacBdRingClone(rxringptr, &bdtemplate, FXMAC_RECV)) + { + LOG_ERR("Error initializing RxBD space\r\n"); + return -EIO; + } + + FXMAC_BD_CLEAR(&bdtemplate); + FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK); + + + /* Create the TxBD ring */ + if (FXmacBdRingCreate(txringptr, (uintptr)dev_data->tx_bdspace, + (uintptr)dev_data->tx_bdspace, ETH_PHYTIUM_BDL_ALIGNMENT, + dev_conf->txbd_count)) + { + return -EIO; + } + + /* We reuse the bd template, as the same one will work for both rx and tx. */ + if(FXmacBdRingClone(txringptr, &bdtemplate, FXMAC_SEND)) + { + return -EIO; + } + + /* init rx buffer */ + for (i = 0; i < dev_conf->rxbd_count; i++) + { + if(FXmacBdRingAlloc(rxringptr, 1, &rxbd)) + { + LOG_ERR("InitDma: Error allocating RxBD\r\n"); + return -ERANGE; + } + + /* Enqueue to HW */ + if(FXmacBdRingToHw(rxringptr, 1, rxbd)) + { + LOG_ERR("Error: committing RxBD to HW\r\n"); + FXmacBdRingUnAlloc(rxringptr, 1, rxbd); + return -ERANGE; + } + + bdindex = FXMAC_BD_TO_INDEX(rxringptr, rxbd); + temp = (u32 *)rxbd; + *temp = 0; + if (bdindex == (dev_conf->rxbd_count - 1)) + { + *temp = 0x00000002; /* Marks last descriptor in receive buffer descriptor list */ + } + temp++; + *temp = 0; /* Clear word 1 in descriptor */ + + FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)(dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size)*bdindex)); + + } + FXmacSetQueuePtr(instance_p, instance_p->tx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_SEND); + FXmacSetQueuePtr(instance_p, instance_p->rx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_RECV); + + return 0; +} + + + +static void eth_phytium_xmac_handle_tx_done(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + FXmac *instance_p; + FXmacBd *txbdset; + FXmacBd *curbdpntr; + u32 n_bds; + FError status; + u32 n_pbufs_freed = 0; + u32 bdindex; + u32 *temp; + instance_p = &dev_data->instance; + FXmacBdRing *txring; + + if (dev_conf->defer_txd_to_queue) { + k_sem_take(&(dev_data->ring_sem), K_FOREVER); + } + txring = &(FXMAC_GET_TXRING((*instance_p))); + while (1) + { + /* obtain processed BD's */ + n_bds = FXmacBdRingFromHwTx(txring, dev_conf->txbd_count, &txbdset); + if (n_bds == 0) + { + break; + } + /* free the processed BD's */ + n_pbufs_freed = n_bds; + curbdpntr = txbdset; + while (n_pbufs_freed > 0) + { + bdindex = FXMAC_BD_TO_INDEX(txring, curbdpntr); + temp = (u32 *)curbdpntr; + *temp = 0; /* Word 0 */ + temp++; + + if (bdindex == (dev_conf->txbd_count - 1)) + { + *temp = 0xC0000000; /* Word 1 ,used/Wrap – marks last descriptor in transmit buffer descriptor list.*/ + } + else + { + *temp = 0x80000000; /* Word 1 , Used – must be zero for GEM to read data to the transmit buffer.*/ + } + + curbdpntr = FXMAC_BD_RING_NEXT(txring, curbdpntr); + n_pbufs_freed--; + + } + + status = FXmacBdRingFree(txring, n_bds, txbdset); + if (status != FT_SUCCESS) + { + LOG_ERR("Failure while freeing in Tx Done ISR\r\n"); + } + } + + if (dev_conf->defer_txd_to_queue) { + k_sem_give(&(dev_data->ring_sem)); + } + + /* Re-enable the TX complete interrupt source */ + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IER_OFFSET,FXMAC_IXR_TXCOMPL_MASK); + + /* Indicate completion to a blocking eth_xlnx_gem_send() call */ + k_sem_give(&dev_data->tx_done_sem); +} + +static void eth_phytium_xmac_tx_done_work(struct k_work *item) +{ + struct eth_phytium_xmac_dev_data *dev_data = CONTAINER_OF(item, struct eth_phytium_xmac_dev_data, tx_done_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_xmac_handle_tx_done(dev); +} + +/** + * @name: eth_phytium_xmac_send + * @msg: Sends an Ethernet frame. The frame is contained in a packet that is managed by the networking stack. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @param {struct net_pkt} *pkt is a pointer to the network packet that contains the data to be sent. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_send(const struct device *dev, struct net_pkt *pkt) +{ + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + + FXmacBd *txbdset, *txbd, *last_txbd = NULL; + FXmacBdRing *txring; + u32 bdindex; + + uint16_t tx_data_length; + uint16_t tx_data_remaining; + void *tx_buffer_offs; + uint32_t bds_reqd; + uint32_t tx_length = 0; + instance_p = &dev_data->instance; + txring = &FXMAC_GET_TXRING((*instance_p)); + + if (!dev_data->started || dev_data->eff_link_speed == LINK_DOWN || + (!net_if_flag_is_set(dev_data->iface, NET_IF_UP))) { +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + return -EIO; + } + + tx_data_length = tx_data_remaining = net_pkt_get_len(pkt); + if (tx_data_length == 0) { + LOG_ERR("%s cannot TX, zero packet length", dev->name); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.errors.tx++; +#endif + return -EINVAL; + } + + bds_reqd = (uint8_t)((tx_data_length + (dev_conf->tx_buffer_size - 1)) / + dev_conf->tx_buffer_size); + + if (dev_conf->defer_txd_to_queue) { + k_sem_take(&(dev_data->ring_sem), K_FOREVER); + } else { + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IDR_OFFSET,FXMAC_IXR_TXCOMPL_MASK); + } + + /* obtain as many BD's */ + if(FXmacBdRingAlloc(txring, bds_reqd, &txbdset)) + { + LOG_ERR("sgsend: Error allocating TxBD\r\n"); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IER_OFFSET,FXMAC_IXR_TXCOMPL_MASK); + return ERR_GENERAL; + } + + if (dev_conf->defer_txd_to_queue) { + k_sem_give(&(dev_data->ring_sem)); + } else { + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IER_OFFSET,FXMAC_IXR_TXCOMPL_MASK); + } + + /* + * Scatter the contents of the network packet's buffer to + * one or more DMA buffers. + */ + net_pkt_cursor_init(pkt); + txbd = txbdset; + while (tx_data_remaining) + { + bdindex = FXMAC_BD_TO_INDEX(txring, txbd); + + /* Calculate the base pointer of the target TX buffer */ + tx_buffer_offs = (void *)(dev_data->first_tx_buffer + + (ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->tx_buffer_size) * bdindex)); + + /* Copy packet data to DMA buffer */ + tx_length = (tx_data_remaining < dev_conf->tx_buffer_size) ? + tx_data_remaining : dev_conf->tx_buffer_size; + net_pkt_read(pkt, (void *)tx_buffer_offs,tx_length); + + FXMAC_BD_SET_ADDRESS_TX(txbd, (uintptr)tx_buffer_offs); + + FXMAC_BD_SET_LENGTH(txbd, tx_length & 0x3FFF); + + last_txbd = txbd; + FXMAC_BD_CLEAR_LAST(txbd); + txbd = FXMAC_BD_RING_NEXT(txring, txbd); + tx_data_remaining -= (tx_data_remaining < dev_conf->tx_buffer_size) ? + tx_data_remaining : dev_conf->tx_buffer_size; + } + FXMAC_BD_SET_LAST(last_txbd); + + if (instance_p->config.caps & FXMAC_CAPS_TAILPTR) + { + bdindex = FXMAC_BD_TO_INDEX(txring, txbd); + } + + FXMAC_BD_CLEAR_TX_USED(last_txbd); + + if(FXmacBdRingToHw(txring, bds_reqd, txbdset)) + { + LOG_ERR("sgsend: Error submitting TxBD\r\n"); + } + + if (instance_p->config.caps & FXMAC_CAPS_TAILPTR) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_TAIL_QUEUE(0), BIT(31)|bdindex); + } + + /* Start transmit */ + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET, + (FXMAC_READREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET) | + FXMAC_NWCTRL_STARTTX_MASK)); + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.bytes.sent += tx_data_length; + dev_data->stats.pkts.tx++; +#endif + + return 0; +} + +static void eth_phytium_xmac_setup_rx_bds(const struct device *dev,FXmacBdRing *rxring) +{ + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + FXmacBd *rxbd; + FError status; + u32 freebds; + u32 bdindex; + u32 *temp; + FXmac *instance_p; + instance_p = &dev_data->instance; + + freebds = FXMAC_BD_RING_GET_FREE_CNT(rxring); + while (freebds > 0) + { + freebds --; + status = FXmacBdRingAlloc(rxring, 1, &rxbd); + if (status != FT_SUCCESS) + { + LOG_ERR("SetupRxBds: Error allocating RxBD\r\n"); + return; + } + status = FXmacBdRingToHw(rxring, 1, rxbd); + if (status != FT_SUCCESS) + { + LOG_ERR("Error committing RxBD to hardware: "); + if (status == FXMAC_ERR_SG_LIST) + { + LOG_ERR("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with FXmacBdRingAlloc()\r\n"); + } + else + { + LOG_ERR("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"); + } + + FXmacBdRingUnAlloc(rxring, 1, rxbd); + return; + } + + + bdindex = FXMAC_BD_TO_INDEX(rxring, rxbd); + temp = (u32 *)rxbd; + if (bdindex == (dev_conf->rxbd_count - 1)) + { + *temp = 0x00000002; /* Mask last descriptor in receive buffer list */ + } + else + { + *temp = 0; + } + temp++; + *temp = 0; + + FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)(dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size)*bdindex)); + + } +} + +static void eth_phytium_xmac_handle_rx_pending(const struct device *dev) +{ + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + FXmacBd *rxbdset, *curbdptr; + FXmacBdRing *rxring; + volatile u32 bd_processed; + u32 k; + u32 bdindex; + FXmac *instance_p; + struct net_pkt *pkt; + uint32_t rx_data_length; + instance_p = &dev_data->instance; + rxring = &FXMAC_GET_RXRING((*instance_p)); + + /* Re-enable the frame received interrupt source */ + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IER_OFFSET,FXMAC_IXR_RXCOMPL_MASK); + + while (1) + { + bd_processed = FXmacBdRingFromHwRx(rxring, dev_conf->rxbd_count, &rxbdset); + if (bd_processed <= 0) + { + break; + } + + for (k = 0, curbdptr = rxbdset; k < bd_processed; k++) + { + bdindex = FXMAC_BD_TO_INDEX(rxring, curbdptr); + rx_data_length = FXMAC_BD_GET_LENGTH(curbdptr); + if(rx_data_length > dev_conf->rx_buffer_size) + { + LOG_ERR("rx_data_length length is error: %u bytes \r\n", + rx_data_length); + goto error_exit; + } + + pkt = net_pkt_rx_alloc_with_buffer(dev_data->iface, rx_data_length, + AF_UNSPEC, 0, K_FOREVER); + if (pkt == NULL) + { + LOG_ERR("RX packet buffer alloc failed: %u bytes", + rx_data_length); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.errors.rx++; + dev_data->stats.error_details.rx_no_buffer_count++; +#endif + /* free up the BD's */ + goto error_exit; + } + + net_pkt_write(pkt, (const void *) + (dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size)*bdindex), + rx_data_length); + + if (net_recv_data(dev_data->iface, pkt) < 0) { + printf("%s RX packet hand-over to IP stack failed", dev->name); + net_pkt_unref(pkt); + } +#ifdef CONFIG_NET_STATISTICS_ETHERNET + else { + dev_data->stats.bytes.received += rx_data_length; + dev_data->stats.pkts.rx++; + } +#endif + curbdptr = FXMAC_BD_RING_NEXT(rxring, curbdptr); + } + FXmacBdRingFree(rxring, bd_processed, rxbdset); + eth_phytium_xmac_setup_rx_bds(dev,rxring); + } + + return; + +error_exit: + printf("eth_phytium_xmac_handle_rx_pending error exit \r\n"); + FXmacBdRingFree(rxring, bd_processed, rxbdset); +} + +static void eth_phytium_xmac_rx_pending_work(struct k_work *item) +{ + struct eth_phytium_xmac_dev_data *dev_data = CONTAINER_OF(item, + struct eth_phytium_xmac_dev_data, rx_pend_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_xmac_handle_rx_pending(dev); +} + + +static void FXmacSendHandler(void *arg) +{ + const struct device *dev = (const struct device *)arg; + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + FXmac *instance_p; + instance_p = &dev_data->instance; + + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_IDR_OFFSET,FXMAC_IXR_TXCOMPL_MASK); + if (dev_conf->defer_txd_to_queue) + { + k_work_submit(&dev_data->tx_done_work); + } + else + { + eth_phytium_xmac_handle_tx_done(dev); + } +} + +static void FXmacRecvHandler(void *arg) +{ + const struct device *dev = (const struct device *)arg; + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + FXmac *instance_p; + instance_p = &dev_data->instance; + + FXMAC_WRITEREG32(instance_p->config.base_address,FXMAC_IDR_OFFSET,FXMAC_IXR_RXCOMPL_MASK); + + if (dev_conf->defer_rxp_to_queue) + { + k_work_submit(&dev_data->rx_pend_work); + } + else + { + printk("recv data \r\n"); + eth_phytium_xmac_handle_rx_pending(dev); + printk("recv data exit \r\n"); + } +} + +/* interrupt */ +static void FXmacHandleDmaTxError( const struct device *dev) +{ + u32 dmacrreg; + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + instance_p = &dev_data->instance; + /* initialize the mac */ + if (FXmacCfgInitialize(instance_p, &instance_p->config)) + { + LOG_ERR("In %s:EmacPs Configuration Failed....\r\n", __func__); + } + + /* set mac address */ + FXmacSetMacAddress(instance_p, (void *)(dev_data->mac_addr), 0); + + dmacrreg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET); + dmacrreg = dmacrreg | (FXMAC_DMACR_ORCE_DISCARD_ON_ERR_MASK); + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET, dmacrreg); + /* setup dma bdl */ + eth_phytium_xmac_setuphandler(dev); + FXmacSetupIsr(dev); + + FXmacStart(instance_p); +} + +static void eth_phytium_xmac_tx_dma_init(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + FXmac *instance_p; + instance_p = &dev_data->instance; + FXmacBd bdtemplate; + FXmacBdRing *txringptr; + + txringptr = &FXMAC_GET_TXRING((*instance_p)); + FXMAC_BD_CLEAR(&bdtemplate); + FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK); + + if (FXmacBdRingCreate(txringptr, (uintptr)dev_data->tx_bdspace, + (uintptr)dev_data->tx_bdspace, ETH_PHYTIUM_BDL_ALIGNMENT, + dev_conf->txbd_count)) + { + LOG_ERR("FXmacBdRingCreate is error"); + return; + } + + FXmacBdRingClone(txringptr, &bdtemplate, FXMAC_SEND); +} + +static void FXmacHandleTxErrors( const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + + instance_p = &dev_data->instance; + + u32 netctrlreg; + + netctrlreg = FXMAC_READREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET); + netctrlreg = netctrlreg & (~FXMAC_NWCTRL_TXEN_MASK); + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET, netctrlreg); + + eth_phytium_xmac_tx_dma_init(dev); + netctrlreg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_NWCTRL_OFFSET); + netctrlreg = netctrlreg | (FXMAC_NWCTRL_TXEN_MASK); + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_NWCTRL_OFFSET, netctrlreg); +} + +void FXmacErrorHandler(void *arg, u8 direction, u32 error_word) +{ + const struct device *dev = (const struct device *)arg; + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + FXmac *instance_p; + instance_p = &dev_data->instance; + + if (error_word != 0) + { + switch (direction) + { + case FXMAC_RECV: + if (error_word & FXMAC_RXSR_HRESPNOK_MASK) + { + LOG_ERR("Receive DMA error\r\n"); + FXmacHandleDmaTxError(dev); + } + if (error_word & FXMAC_RXSR_RXOVR_MASK) + { + LOG_ERR("Receive over run\r\n"); + FXmacRecvHandler((void *)dev); + } + if (error_word & FXMAC_RXSR_BUFFNA_MASK) + { + LOG_ERR("Receive buffer not available\r\n"); + FXmacRecvHandler((void *)dev); + } + break; + case FXMAC_SEND: + if (error_word & FXMAC_TXSR_HRESPNOK_MASK) + { + LOG_ERR("Transmit DMA error\r\n"); + FXmacHandleDmaTxError(dev); + } + if (error_word & FXMAC_TXSR_URUN_MASK) + { + LOG_ERR("Transmit under run\r\n"); + FXmacHandleTxErrors(dev); + } + if (error_word & FXMAC_TXSR_BUFEXH_MASK) + { + LOG_ERR("Transmit buffer exhausted\r\n"); + FXmacHandleTxErrors(dev); + } + if (error_word & FXMAC_TXSR_RXOVR_MASK) + { + LOG_ERR("Transmit retry excessed limits\r\n"); + FXmacHandleTxErrors(dev); + } + if (error_word & FXMAC_TXSR_FRAMERX_MASK) + { + LOG_ERR("Transmit collision\r\n"); + if (dev_conf->defer_txd_to_queue) { + k_work_submit(&dev_data->tx_done_work); + } + else + { + eth_phytium_xmac_handle_tx_done(dev); + } + } + break; + } + } +} + +#ifdef CONFIG_NET_STATISTICS_ETHERNET +/** + * @name: eth_phytium_xmac_stats + * @msg: Retrieves the Ethernet statistics for the device. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {struct net_stats_eth} * A pointer to the statistics structure. + */ +static struct net_stats_eth *eth_phytium_xmac_stats(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + + return &dev_data->stats; +} +#endif + +/** + * @name: FXmacSetupIsr + * @msg: Sets up the interrupt service routine handlers for transmit, receive, and error events. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + */ +static void FXmacSetupIsr(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + /* Setup callbacks */ + FXmac *instance_p; + instance_p = &dev_data->instance; + + FXmacSetHandler(instance_p, FXMAC_HANDLER_DMASEND, FXmacSendHandler, (void *)dev); + FXmacSetHandler(instance_p, FXMAC_HANDLER_DMARECV, FXmacRecvHandler,(void *) (void *)dev); + FXmacSetHandler(instance_p, FXMAC_HANDLER_ERROR, FXmacErrorHandler, (void *)dev); +} + +/** + * @name: eth_phytium_xmac_start_device + * @msg: Starts the Ethernet device, enabling packet transmission and reception. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_start_device(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + /* Setup callbacks */ + if (dev_data->started) { + return 0; + } + dev_data->started = true; + + FXmac *instance_p; + instance_p = &dev_data->instance; + FXmacStart(instance_p); + return 0; +} + +/** + * @name: eth_phytium_xmac_stop_device + * @msg: Stops the Ethernet device, disabling packet transmission and reception. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_stop_device(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + FXmac *instance_p; + instance_p = &dev_data->instance; + + if (!dev_data->started) { + return 0; + } + dev_data->started = false; + + /* Cancel the delayed work that polls the link state */ + if (k_work_delayable_remaining_get(&dev_data->phy_poll_delayed_work) != 0) + { + k_work_cancel_delayable(&dev_data->phy_poll_delayed_work); + } + + FXmacStop(instance_p); + + return 0; +} + +/** + * @name: eth_phytium_xmac_isr + * @msg: Interrupt service routine for handling all interrupts from the Ethernet device. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + */ +static void eth_phytium_xmac_isr(const struct device *dev) +{ + u32 reg_isr; + u32 reg_temp; + u32 reg_ctrl; + + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + /* Setup callbacks */ + FXmac *instance_p; + instance_p = &dev_data->instance; + + reg_isr = FXMAC_READREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET); + { + if ((reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U) + { + /* Clear TX status register TX complete indication but preserve + * error bits if there is any */ + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_TXSR_OFFSET, + ((u32)FXMAC_TXSR_TXCOMPL_MASK | + (u32)FXMAC_TXSR_USEDREAD_MASK)); + if (instance_p->send_irq_handler) + { + /* code */ + instance_p->send_irq_handler(instance_p->send_args); + } + /* add */ + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXCOMPL_MASK); + } + } + + /* Transmit error conditions interrupt */ + if (((reg_isr & FXMAC_IXR_TX_ERR_MASK) != 0x00000000U) && + (!(reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U)) + { + /* Clear TX status register */ + reg_temp = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET); + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET, reg_temp); + if (instance_p->error_irq_handler) + { + instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND, reg_temp); + } + /* add */ + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TX_ERR_MASK); + } + } + + /* add restart */ + if ((reg_isr & FXMAC_IXR_TXUSED_MASK) != 0x00000000U) + { + /* add */ + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXUSED_MASK); + } + if (instance_p->restart_handler) + { + instance_p->restart_handler(instance_p->restart_args); + } + } + + /* link changed */ + if ((reg_isr & FXMAC_IXR_LINKCHANGE_MASK) != 0x00000000U) + { + if (instance_p->link_change_handler) + { + instance_p->link_change_handler(instance_p->link_change_args); + } + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_LINKCHANGE_MASK); + } + } + } + + + { + /* Receive complete interrupt */ + if ((reg_isr & FXMAC_IXR_RXCOMPL_MASK) != 0x00000000U) + { + /* Clear RX status register RX complete indication but preserve + * error bits if there is any */ + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_RXSR_OFFSET, + ((u32)FXMAC_RXSR_FRAMERX_MASK | + (u32)FXMAC_RXSR_BUFFNA_MASK)); + instance_p->recv_irq_handler(instance_p->recv_args); + /* add */ + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXCOMPL_MASK); + } + } + + /* Receive error conditions interrupt */ + if ((reg_isr & FXMAC_IXR_RX_ERR_MASK) != 0x00000000U) + { + /* Clear RX status register */ + reg_temp = FXMAC_READREG32(instance_p->config.base_address, + FXMAC_RXSR_OFFSET); + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_RXSR_OFFSET, reg_temp); + if ((reg_isr & FXMAC_IXR_RXUSED_MASK) != 0x00000000U) + { + reg_ctrl = FXMAC_READREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET); + reg_ctrl |= (u32)FXMAC_NWCTRL_FLUSH_DPRAM_MASK; + /* add */ + reg_ctrl &= (u32)(~FXMAC_NWCTRL_RXEN_MASK); + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET, reg_ctrl); + /* add */ + reg_ctrl |= (u32)FXMAC_NWCTRL_RXEN_MASK; + FXMAC_WRITEREG32(instance_p->config.base_address, + FXMAC_NWCTRL_OFFSET, reg_ctrl); + + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXUSED_MASK); + } + } + /* add */ + if ((reg_isr & FXMAC_IXR_RXOVR_MASK) != 0x00000000U) + { + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXOVR_MASK); + } + } + /* add */ + if ((reg_isr & FXMAC_IXR_HRESPNOK_MASK) != 0x00000000U) + { + if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_HRESPNOK_MASK); + } + } + if (reg_temp != 0) + { + instance_p->error_irq_handler(instance_p->error_args, + FXMAC_RECV, reg_temp); + } + } + } +} + +/** + * @name: eth_phytium_xmac_iface_init + * @msg: Initializes the network interface for the Ethernet driver. Sets the link address and registers the Ethernet interface with the network stack. + * @param {struct net_if} *iface is a pointer to the network interface structure. + */ +static void eth_phytium_xmac_iface_init(struct net_if *iface) +{ + const struct device *dev = net_if_get_device(iface); + const struct eth_phytium_xmac_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_dev_data *dev_data = dev->data; + + /* Set the initial contents of the current instance's run-time data */ + dev_data->iface = iface; + net_if_set_link_addr(iface, dev_data->mac_addr, 6, NET_LINK_ETHERNET); + ethernet_init(iface); + net_if_carrier_off(iface); + + /* + * Initialize the (delayed) work items for RX pending, TX done + * and PHY status polling handlers + */ + k_work_init(&dev_data->tx_done_work, eth_phytium_xmac_tx_done_work); + k_work_init(&dev_data->rx_pend_work, eth_phytium_xmac_rx_pending_work); + k_work_init_delayable(&dev_data->phy_poll_delayed_work, + eth_phytium_xmac_poll_phy); + + /* Initialize TX completion semaphore */ + k_sem_init(&dev_data->tx_done_sem, 0, 1); + + /* + * Initialize semaphores in the RX/TX BD rings which have not + * yet been initialized + */ + k_sem_init(&dev_data->ring_sem, 1, 1); + /* RX BD ring semaphore is not required at the time being */ + + /* Initialize the device's interrupt */ + dev_conf->config_func(dev); + + /* Submit initial PHY status polling delayed work */ + k_work_reschedule(&dev_data->phy_poll_delayed_work, K_NO_WAIT); + +} + +/** + * @name: eth_phytium_xmac_dev_init + * @msg: Initializes the Ethernet device, including hardware configuration and MAC address setting. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_dev_init(const struct device *dev) +{ + struct eth_phytium_xmac_dev_data *dev_data = (struct eth_phytium_xmac_dev_data *)dev->data; + struct eth_phytium_xmac_dev_cfg *dev_conf = (struct eth_phytium_xmac_dev_cfg *)dev->config; + FXmacConfig mac_config; + FXmac *instance_p; + uint32_t xmac_options; + uint32_t dmacrreg; + int ret; + + /* init base */ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + + /* config init */ + mac_config.base_address = DEVICE_MMIO_GET(dev); + mac_config.instance_id = 0; + + ret = eth_phytium_xmac_config_convert(dev_conf,&mac_config,&xmac_options); + if(ret) + { + return -EINVAL; + } + + instance_p = &dev_data->instance; + if(FXmacCfgInitialize(instance_p, &mac_config)) + { + return -EIO; + } + + FXmacSetOptions(instance_p, xmac_options, 0); + + /* set mac address */ + if(FXmacSetMacAddress(instance_p, (void *)(dev_data->mac_addr), 0)) + { + return -EIO; + } + + if(mac_config.interface != FXMAC_PHY_INTERFACE_MODE_USXGMII) + { + /* initialize phy */ + if(FXmacPhyInit(instance_p, instance_p->config.speed, instance_p->config.duplex, instance_p->config.auto_neg,XMAC_PHY_RESET_ENABLE)) + { + LOG_WRN("FXmacPhyInit is error \r\n"); + } + } + + FXmacSelectClk(instance_p); + FXmacInitInterface(instance_p); + + /* initialize dma */ + dmacrreg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET); + dmacrreg &= ~(FXMAC_DMACR_BLENGTH_MASK); + dmacrreg = dmacrreg | FXMAC_DMACR_INCR16_AHB_AXI_BURST; /* Attempt to use bursts of up to 16. */ + FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET, dmacrreg); + /* setup dma bdl */ + eth_phytium_xmac_setuphandler(dev); + instance_p->mask = ((u32)FXMAC_IXR_TX_ERR_MASK + | (u32)FXMAC_IXR_RX_ERR_MASK + | (u32)FXMAC_IXR_RXCOMPL_MASK + | (u32)FXMAC_IXR_TXCOMPL_MASK); + /* setup tx、rx intr */ + FXmacSetupIsr(dev); + + return 0; +} + + + + diff --git a/drivers/ethernet/eth_phytium_xmac.h b/drivers/ethernet/eth_phytium_xmac.h new file mode 100644 index 0000000000000000000000000000000000000000..33cc1ecb7134e676abacbb3745ee00d134813946 --- /dev/null +++ b/drivers/ethernet/eth_phytium_xmac.h @@ -0,0 +1,117 @@ +#ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_XMAC_H_ +#define _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_XMAC_H_ + +#include "fxmac_bd.h" + +/* DMA memory area instantiation macro */ +#define ETH_PHYTIUM_XMAC_DMA_AREA_INST(port) \ +static struct eth_phytium_dma_area_gem##port eth_phytium_xmac##port##_dma_area\ + __aligned(4096); + +/* DMA memory area declaration macro */ +#define ETH_PHYTIUM_XMAC_DMA_AREA_DECL(port) \ +struct eth_phytium_dma_area_gem##port {\ + uint8_t rx_bd[DT_INST_PROP(port, rx_buffer_descriptors) * (u32)sizeof(FXmacBd)] __attribute__((aligned(256))) ;\ + uint8_t tx_bd[DT_INST_PROP(port, tx_buffer_descriptors) * (u32)sizeof(FXmacBd)] __attribute__((aligned(256)));\ + uint8_t rx_buffer\ + [DT_INST_PROP(port, rx_buffer_descriptors)]\ + [((DT_INST_PROP(port, rx_buffer_size)\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))];\ + uint8_t tx_buffer\ + [DT_INST_PROP(port, tx_buffer_descriptors)]\ + [((DT_INST_PROP(port, tx_buffer_size)\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))];\ +}; + + +/* RX/TX BD Ring initialization macro */ +#define ETH_PHYTIUM_XMAC_INIT_BD_RING(port) \ + dev_data->rx_bdspace = &(eth_phytium_xmac##port##_dma_area.rx_bd[0]);\ + dev_data->tx_bdspace = &(eth_phytium_xmac##port##_dma_area.tx_bd[0]);\ + dev_data->first_rx_buffer = (uint8_t *)eth_phytium_xmac##port##_dma_area.rx_buffer;\ + dev_data->first_rx_buffer_virt = dev_data->first_rx_buffer ;\ + dev_data->first_tx_buffer = (uint8_t *)eth_phytium_xmac##port##_dma_area.tx_buffer; \ + dev_data->first_tx_buffer_virt =dev_data->first_tx_buffer ; + + + + +#define ETH_PHYTIUM_XMAC_NET_DEV_INIT(port) \ +ETH_NET_DEVICE_DT_INST_DEFINE(port,\ + eth_phytium_xmac_dev_init,\ + NULL,\ + ð_phytium_xmac##port##_dev_data,\ + ð_phytium_xmac##port##_dev_cfg,\ + CONFIG_ETH_INIT_PRIORITY,\ + ð_phytium_xmac_apis,\ + NET_ETH_MTU); + + + +/* Device configuration data declaration macro */ +#define ETH_PHYTIUM_XMAC_DEV_CONFIG(port) \ +static const struct eth_phytium_xmac_dev_cfg eth_phytium_xmac##port##_dev_cfg = {\ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)), \ + .instance_id = port, \ + .config_func = eth_phytium_xmac##port##_irq_config,\ + .pll_clock_frequency = DT_INST_PROP(port, clock_frequency),\ + .phy_poll_interval = DT_INST_PROP(port, phy_poll_interval),\ + .defer_rxp_to_queue = !DT_INST_PROP(port, handle_rx_in_isr),\ + .defer_txd_to_queue = DT_INST_PROP(port, handle_tx_in_workq),\ + .rxbd_count = (uint8_t)\ + (DT_INST_PROP(port, rx_buffer_descriptors)),\ + .txbd_count = (uint8_t)\ + (DT_INST_PROP(port, tx_buffer_descriptors)),\ + .rx_buffer_size = (((uint16_t)(DT_INST_PROP(port, rx_buffer_size)) +\ + (ETH_PHYTIUM_BUFFER_ALIGNMENT-1)) & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT-1)),\ + .tx_buffer_size = (((uint16_t)(DT_INST_PROP(port, tx_buffer_size)) +\ + (ETH_PHYTIUM_BUFFER_ALIGNMENT-1)) & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT-1)),\ + .phy_speed = DT_INST_PROP(port, phy_speed),\ + .interface_mode = DT_INST_PROP(port, interface_mode),\ + .dma_brust_length = DT_INST_PROP(port, dma_brust_length),\ + .max_queue_num = DT_INST_PROP(port, max_queue_num),\ + .phy_autonegotiation = DT_INST_PROP(port, phy_autonegotiation),\ + .enable_fdx = DT_INST_PROP(port, enable_fdx),\ + .enable_jumbo = DT_INST_PROP(port, enable_jumbo),\ + .enable_ucast_hash = DT_INST_PROP(port, enable_ucast_hash),\ + .copy_all_frames = DT_INST_PROP(port, copy_all_frames),\ + .disable_reject_fcs_crc_errors = DT_INST_PROP(port, disable_reject_fcs_crc_errors),\ + .enable_mcast_hash = DT_INST_PROP(port, enable_mcast_hash),\ +}; + +/* Device run-time data declaration macro */ +#define ETH_PHYTIUM_XMAC_DEV_DATA(port) \ +static struct eth_phytium_xmac_dev_data eth_phytium_xmac##port##_dev_data = {\ + .mac_addr = DT_INST_PROP(port, local_mac_address),\ + .started = 0,\ + .eff_link_speed = LINK_DOWN,\ + .phy_addr = 0,\ + .phy_id = 0,\ + .first_rx_buffer = NULL,\ + .first_tx_buffer = NULL\ +}; + +/* Interrupt configuration function macro */ +#define ETH_PHYTIUM_XMAC_CONFIG_IRQ_FUNC(port) \ +static void eth_phytium_xmac##port##_irq_config(const struct device *dev)\ +{\ + ARG_UNUSED(dev);\ + IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority),\ + eth_phytium_xmac_isr, DEVICE_DT_INST_GET(port), 0);\ + irq_enable(DT_INST_IRQN(port));\ +} + + +/* Top-level device initialization macro - bundles all of the above */ +#define ETH_PHYTIUM_XMAC_INITIALIZE(port) \ +ETH_PHYTIUM_XMAC_CONFIG_IRQ_FUNC(port);\ +ETH_PHYTIUM_XMAC_DEV_CONFIG(port);\ +ETH_PHYTIUM_XMAC_DEV_DATA(port);\ +ETH_PHYTIUM_XMAC_DMA_AREA_DECL(port);\ +ETH_PHYTIUM_XMAC_DMA_AREA_INST(port);\ +ETH_PHYTIUM_XMAC_NET_DEV_INIT(port);\ + + +#endif diff --git a/drivers/ethernet/eth_phytium_xmac_v2.c b/drivers/ethernet/eth_phytium_xmac_v2.c new file mode 100644 index 0000000000000000000000000000000000000000..fd677fc215a7952dec51a0b658e15bcf51af7072 --- /dev/null +++ b/drivers/ethernet/eth_phytium_xmac_v2.c @@ -0,0 +1,1319 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +#include "fparameters.h" +#include "fxmac_msg.h" +#include "fxmac_msg_hw.h" +#include "fxmac_msg_bdring.h" +#include "fxmac_msg_phy.h" +#include "fxmac_msg_common.h" +#include "eth_ieee_reg.h" +#include "eth_phytium_xmac_v2.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define LOG_MODULE_NAME phytium_xmac_v2 +#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL +#include +LOG_MODULE_REGISTER(LOG_MODULE_NAME); + +#define DT_DRV_COMPAT phytium_xmac_v2 + +/* dma buffer */ +#define ETH_PHYTIUM_BDL_ALIGNMENT 256 +#define ETH_PHYTIUM_BUFFER_ALIGNMENT ETH_PHYTIUM_BDL_ALIGNMENT +#define ETH_ALIGNMENT_OFFSET_DEFINED(buffer_size) ((buffer_size\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1)) + +/* IRQ handler function type */ +typedef void (*eth_phytiium_xmac_v2_config_irq_t)(const struct device *dev); + +typedef enum +{ + FXMAC_MSG_LWIP_PORT_INTERFACE_SGMII = 0, + FXMAC_MSG_LWIP_PORT_INTERFACE_RMII, + FXMAC_MSG_LWIP_PORT_INTERFACE_RGMII, + FXMAC_MSG_LWIP_PORT_INTERFACE_USXGMII, + FXMAC_MSG_LWIP_PORT_INTERFACE_LENGTH +} FXmacMsgLwipPortInterface; + + +#define FXMAC_MSG_PHY_SPEED_10M 10 +#define FXMAC_MSG_PHY_SPEED_100M 100 +#define FXMAC_MSG_PHY_SPEED_1000M 1000 +#define FXMAC_MSG_PHY_SPEED_10G 10000 + +/* configuration */ +#define FXMAC_MSG_LWIP_PORT_CONFIG_JUMBO BIT(0) +#define FXMAC_MSG_LWIP_PORT_CONFIG_MULTICAST_ADDRESS_FILITER BIT(1) /* Allow multicast address filtering */ +#define FXMAC_MSG_LWIP_PORT_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */ +#define FXMAC_MSG_LWIP_PORT_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */ +#define FXMAC_MSG_LWIP_PORT_CONFIG_UNICAST_ADDRESS_FILITER BIT(5) /* Allow unicast address filtering */ + +/* phy link */ +enum eth_phytium_link_speed { + /* The values of this enum are consecutively numbered */ + LINK_DOWN = 0, + LINK_10MBIT, + LINK_100MBIT, + LINK_1GBIT +}; + +#define FXMAC_MSG_BD_TO_INDEX(ringptr, bdptr) (((uintptr)bdptr - (uintptr)(ringptr)->base_bd_addr) / (ringptr)->separation) + +struct eth_phytium_xmac_v2_dev_cfg { + DEVICE_MMIO_ROM; + uint32_t instance_id; /* */ + eth_phytiium_xmac_v2_config_irq_t config_func; + uint32_t pll_clock_frequency; + + uint32_t phy_poll_interval; + uint8_t defer_rxp_to_queue; + uint8_t defer_txd_to_queue; + + uint8_t rxbd_count; /* rx bdl count */ + uint8_t txbd_count; /* tx bdl count */ + uint16_t rx_buffer_size; /* per buffer size */ + uint16_t tx_buffer_size; + + /* dtc defined */ + uint32_t phy_speed; /* FXMAC_PHY_SPEED_XX */ + uint32_t interface_mode; /* followed by FXmacMsgLwipPortInterface */ + uint32_t dma_brust_length; + uint32_t max_queue_num; /* Number of Xmac Controller Queues */ + bool phy_autonegotiation : 1; + bool enable_fdx : 1; + bool enable_jumbo : 1; + bool enable_ucast_hash :1; + bool copy_all_frames :1; + bool disable_reject_fcs_crc_errors:1; + bool enable_mcast_hash :1; + +}; + + +struct eth_phytium_xmac_v2_dev_data { + DEVICE_MMIO_RAM; /* used for controller base address */ + struct net_if *iface; + FXmacMsgCtrl instance; + uint8_t mac_addr[6]; + enum eth_phytium_link_speed eff_link_speed; + struct k_work tx_done_work; + struct k_work rx_pend_work; + struct k_sem tx_done_sem; + + struct k_sem ring_sem; + + uint8_t phy_addr; + uint32_t phy_id; + struct k_work_delayable phy_poll_delayed_work; + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + struct net_stats_eth stats; +#endif + + uint8_t *rx_bdspace; + uint8_t *rx_bdspace_virt; + uint8_t *tx_bdspace; + uint8_t *tx_bdspace_virt; + + uint8_t *first_rx_buffer; + uint8_t *first_rx_buffer_virt; + uint8_t *first_tx_buffer; + uint8_t *first_tx_buffer_virt; + + bool started; +}; + + +static int eth_phytium_xmac_v2_dev_init(const struct device *dev); +static void eth_phytium_xmac_v2_iface_init(struct net_if *iface); +static enum ethernet_hw_caps eth_phytium_xmac_v2_get_capabilities(const struct device *dev); +static int eth_phytium_xmac_v2_send(const struct device *dev, struct net_pkt *pkt); +static int eth_phytium_xmac_v2_start_device(const struct device *dev); +static int eth_phytium_xmac_v2_stop_device(const struct device *dev); +#ifdef CONFIG_NET_STATISTICS_ETHERNET +static struct net_stats_eth *eth_phytium_xmac_v2_stats(const struct device *dev); +#endif + +static void eth_phytium_xmac_v2_isr(const struct device *dev); + +static const struct ethernet_api eth_phytium_xmac_v2_apis = { + .iface_api.init = eth_phytium_xmac_v2_iface_init, + .get_capabilities = eth_phytium_xmac_v2_get_capabilities, + .send = eth_phytium_xmac_v2_send, + .start = eth_phytium_xmac_v2_start_device, + .stop = eth_phytium_xmac_v2_stop_device, +#if defined(CONFIG_NET_STATISTICS_ETHERNET) + .get_stats = eth_phytium_xmac_v2_stats, +#endif +}; + + +/* + * Insert the configuration & run-time data for all GEM instances which + * are enabled in the device tree of the current target board. + */ +DT_INST_FOREACH_STATUS_OKAY(ETH_PHYTIUM_XMAC_V2_INITIALIZE) + + +static void FXmacMsgSetupIsr(const struct device *dev); + +static uint32_t phy_autoneg_status(FXmacMsgCtrl *xmac_p, uint32_t phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + status = FXmacMsgMdioDataReadC22(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET); + + if (status & PHY_STATUS_AUTONEGOTIATE_COMPLETE) + return 1; + return 0; +} + +/** + * @name: phy_link_detect + * @msg: Get current link status + * @note: + * @param {FXmacMsgCtrl} *fxmac_p + * @param {u32} phy_addr + * @return {*} 1 is link up , 0 is link down + */ +static u32 phy_link_detect(FXmacMsgCtrl *xmac_p, u32 phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + status = FXmacMsgMdioDataReadC22(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET); + + if (status & PHY_STAT_LINK_STATUS) + return 1; + return 0; +} + +FXmacMsgLinkStatus FXmacMsgRgmiiLinkDetect(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + u32 phy_link_status; + + + phy_link_status = phy_link_detect(instance_p, instance_p->phy_address); + + if ((instance_p->link_status == FXMAC_MSG_LINKUP) && (!phy_link_status)) + instance_p->link_status = FXMAC_MSG_LINKDOWN; + + switch (instance_p->link_status) + { + case FXMAC_MSG_LINKUP: + return FXMAC_MSG_LINKUP; + case FXMAC_MSG_LINKDOWN: + instance_p->link_status = FXMAC_MSG_NEGOTIATING; + LOG_DBG("Ethernet Link down"); + return FXMAC_MSG_LINKDOWN; + case FXMAC_MSG_NEGOTIATING: + if ((phy_link_status == FXMAC_MSG_LINKUP) && phy_autoneg_status(instance_p, instance_p->phy_address)) + { + if(FXmacMsgPhyInit(instance_p, instance_p->config.speed, instance_p->config.duplex, instance_p->config.auto_neg, FXMAC_MSG_PHY_RESET_DISABLE)) + { + return FXMAC_MSG_LINKDOWN; + } + + FXmacMsgInterfaceConfig(instance_p, 0); + + /* Initiate Phy setup to get link speed */ + instance_p->link_status = FXMAC_MSG_LINKUP; + LOG_DBG("Ethernet Link up"); + return FXMAC_MSG_LINKUP; + } + return FXMAC_MSG_LINKDOWN; + default: + return FXMAC_MSG_LINKDOWN; + } +} + +FXmacMsgLinkStatus FXmacMsgSgmiiLinkDetect(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *xmac_p; + u32 ctrl; + u32 link, link_status; + xmac_p = &dev_data->instance; + + ctrl = FXMAC_MSG_READ(xmac_p, FXMAC_MSG_PCS_AN_LP); + link = (ctrl & BIT(FXMAC_MSG_PCS_LINK_PARTNER_NEXT_PAGE_INDEX)) >> FXMAC_MSG_PCS_LINK_PARTNER_NEXT_PAGE_INDEX; + + switch (link) + { + case 0: + link_status = FXMAC_MSG_LINKDOWN; + break; + case 1: + link_status = FXMAC_MSG_LINKUP; + break; + default: + LOG_ERR("link status is error 0x%x \r\n", link); + return FXMAC_MSG_LINKDOWN; + } + + if (link_status == FXMAC_MSG_LINKUP) + { + if (link_status != xmac_p->link_status) + { + xmac_p->link_status = FXMAC_MSG_NEGOTIATING; + LOG_INF("need NEGOTIATING"); + } + } + else + { + xmac_p->link_status = FXMAC_MSG_LINKDOWN; + } + + if (xmac_p->link_status == FXMAC_MSG_NEGOTIATING) + { + /* renegotiate */ + if (FXmacMsgPhyInit(xmac_p, xmac_p->config.speed, xmac_p->config.duplex, xmac_p->config.auto_neg, FXMAC_MSG_PHY_RESET_DISABLE)) + { + LOG_ERR("FXmacMsgPhyInit is error \r\n"); + return FXMAC_MSG_LINKDOWN; + } + else + { + FXmacMsgInterfaceConfig(xmac_p, 0); + xmac_p->link_status = FXMAC_MSG_LINKUP; + return FXMAC_MSG_LINKUP; + } + } + return xmac_p->link_status; +} + +static void eth_phytium_xmac_v2_poll_phy(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct eth_phytium_xmac_v2_dev_data *dev_data = CONTAINER_OF(dwork, struct eth_phytium_xmac_v2_dev_data, phy_poll_delayed_work); + const struct device *dev = net_if_get_device(dev_data->iface); + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + FXmacMsgLinkStatus link_status = FXMAC_MSG_LINKDOWN; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + if(instance_p->config.interface == FXMAC_MSG_PHY_INTERFACE_MODE_SGMII) + { + link_status = FXmacMsgSgmiiLinkDetect(dev); + } + else if((instance_p->config.interface == FXMAC_MSG_PHY_INTERFACE_MODE_RMII) || (instance_p->config.interface == FXMAC_MSG_PHY_INTERFACE_MODE_RGMII)) + { + link_status = FXmacMsgRgmiiLinkDetect(dev); + } + + if(link_status == FXMAC_MSG_LINKDOWN) + { + dev_data->eff_link_speed = LINK_DOWN; + net_eth_carrier_off(dev_data->iface); + + LOG_WRN("%s link down", dev->name); + } + else if(link_status == FXMAC_MSG_LINKUP) + { + switch(instance_p->config.speed) + { + case FXMAC_MSG_SPEED_10: + dev_data->eff_link_speed = LINK_10MBIT; + break; + case FXMAC_MSG_SPEED_100: + dev_data->eff_link_speed = LINK_100MBIT; + break; + case FXMAC_MSG_SPEED_1000: + dev_data->eff_link_speed = LINK_1GBIT; + break; + } + net_eth_carrier_on(dev_data->iface); + } + + k_work_reschedule(&dev_data->phy_poll_delayed_work, K_MSEC(dev_conf->phy_poll_interval)); +} + +/** + * @name: eth_phytium_xmac_v2_get_capabilities + * @msg: Reports the hardware capabilities of the Ethernet device, such as supported speeds and duplex modes. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {enum ethernet_hw_caps} A bitmask of supported features defined in `enum ethernet_hw_caps`. + */ +static enum ethernet_hw_caps eth_phytium_xmac_v2_get_capabilities(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_cfg *dev_cfg = (struct eth_phytium_xmac_v2_dev_cfg *)dev->config; + enum ethernet_hw_caps caps = (enum ethernet_hw_caps)0; + + switch (dev_cfg->phy_speed) + { + case FXMAC_MSG_PHY_SPEED_10M: + caps |= ETHERNET_LINK_10BASE_T; + break; + case FXMAC_MSG_PHY_SPEED_100M: + caps |= (ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + case FXMAC_MSG_PHY_SPEED_1000M: + caps |= (ETHERNET_LINK_1000BASE_T | + ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + case FXMAC_MSG_PHY_SPEED_10G: + caps |= (ETHERNET_LINK_1000BASE_T | + ETHERNET_LINK_100BASE_T | + ETHERNET_LINK_10BASE_T); + break; + } + + if (dev_cfg->enable_fdx) + { + caps |= ETHERNET_DUPLEX_SET; + } + + if (dev_cfg->copy_all_frames) + { + caps |= ETHERNET_PROMISC_MODE; + } + return caps; +} + +static int eth_phytium_xmac_config_convert(struct eth_phytium_xmac_v2_dev_cfg *dev_conf, FXmacMsgConfig *mac_config, uint32_t *options) +{ + *options = 0; + switch (dev_conf->interface_mode) + { + case FXMAC_MSG_LWIP_PORT_INTERFACE_SGMII: + mac_config->interface = FXMAC_MSG_PHY_INTERFACE_MODE_SGMII; + LOG_INF("SGMII select"); + break; + case FXMAC_MSG_LWIP_PORT_INTERFACE_RMII: + mac_config->interface = FXMAC_MSG_PHY_INTERFACE_MODE_RMII; + LOG_INF("RMII select"); + break; + case FXMAC_MSG_LWIP_PORT_INTERFACE_RGMII: + LOG_INF("RGMII select"); + mac_config->interface = FXMAC_MSG_PHY_INTERFACE_MODE_RGMII; + break; + case FXMAC_MSG_LWIP_PORT_INTERFACE_USXGMII: + LOG_INF("USXGMII select"); + mac_config->interface = FXMAC_MSG_PHY_INTERFACE_MODE_USXGMII; + break; + default: + return -EINVAL; + } + + switch (dev_conf->phy_speed) + { + case FXMAC_MSG_PHY_SPEED_10M: + mac_config->speed = FXMAC_MSG_SPEED_10; + break; + case FXMAC_MSG_PHY_SPEED_100M: + mac_config->speed = FXMAC_MSG_SPEED_100; + break; + case FXMAC_MSG_PHY_SPEED_1000M: + mac_config->speed = FXMAC_MSG_SPEED_1000; + break; + case FXMAC_MSG_PHY_SPEED_10G: + LOG_INF("select FXMAC_MSG_PHY_SPEED_10G"); + mac_config->speed = FXMAC_MSG_SPEED_10000; + break; + default: + return -EINVAL; + } + + mac_config->duplex = dev_conf->enable_fdx? 1:0; /* 1 is full-duplex , 0 is half-duplex */ + mac_config->auto_neg = dev_conf->phy_autonegotiation; /* Enable auto-negotiation - when set active high, autonegotiation operation is enabled. */ + mac_config->pclk_hz = dev_conf->pll_clock_frequency; + mac_config->max_queue_num = dev_conf->max_queue_num; /* Number of Xmac Controller Queues */ + mac_config->tx_queue_id = 0; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */ + mac_config->rx_queue_id = 0; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */ + mac_config->dma_brust_length = dev_conf->dma_brust_length; /* burst length */ + mac_config->network_default_config = FXMAC_MSG_DEFAULT_OPTIONS; +#if defined(FXMAC_MSG_CAPS) + mac_config->caps = FXMAC_MSG_CAPS; /* used to configure tail ptr feature */ +#else + mac_config->caps = 0; +#endif + + /* options */ + if(dev_conf->enable_jumbo) + { + *options |= FXMAC_MSG_JUMBO_ENABLE_OPTION; + } + + if(dev_conf->enable_ucast_hash) + { + *options |= FXMAC_MSG_UNICAST_OPTION; + } + + if(dev_conf->enable_mcast_hash) + { + *options |= FXMAC_MSG_MULTICAST_OPTION; + } + + if(dev_conf->copy_all_frames) + { + *options |= FXMAC_MSG_PROMISC_OPTION; + } + + if(dev_conf->disable_reject_fcs_crc_errors) + { + *options |= FXMAC_MSG_FCS_STRIP_OPTION; + } + + return 0; +} + +/* dma init */ +static int eth_phytium_xmac_v2_init_dma(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_cfg *dev_conf = (struct eth_phytium_xmac_v2_dev_cfg *)dev->config; + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *instance_p; + + FXmacMsgBd bdtemplate; + FXmacMsgBdRing *rxringptr, *txringptr; + FXmacMsgBd *rxbd; + int i; + u32 bdindex; + u32 *temp; + instance_p = &dev_data->instance; + /* init buffer to data */ + /* Initial configuration of the RX/TX BD rings */ + DT_INST_FOREACH_STATUS_OKAY(ETH_PHYTIUM_XMAC_V2_INIT_BD_RING) + rxringptr = &FXMAC_MSG_GET_RXRING((*instance_p)); + txringptr = &FXMAC_MSG_GET_TXRING((*instance_p)); + + /* Setup RxBD space. */ + FXMAC_MSG_BD_CLEAR(&bdtemplate); + + /* Create the RxBD ring */ + if(FXmacMsgBdRingCreate(rxringptr, (uintptr)dev_data->rx_bdspace, + (uintptr)dev_data->rx_bdspace, + ETH_PHYTIUM_BDL_ALIGNMENT, + dev_conf->rxbd_count)) + { + LOG_ERR("Error setting up RxBD space\r\n"); + return -EIO; + } + + if(FXmacMsgBdRingClone(rxringptr, &bdtemplate, FXMAC_MSG_RECV)) + { + LOG_ERR("Error initializing RxBD space\r\n"); + return -EIO; + } + + FXMAC_MSG_BD_CLEAR(&bdtemplate); + FXMAC_MSG_BD_SET_STATUS(&bdtemplate, FXMAC_MSG_TXBUF_USED_MASK); + + /* Create the TxBD ring */ + if (FXmacMsgBdRingCreate(txringptr, (uintptr)dev_data->tx_bdspace, (uintptr)dev_data->tx_bdspace, ETH_PHYTIUM_BDL_ALIGNMENT, dev_conf->txbd_count)) + { + return -EIO; + } + + /* We reuse the bd template, as the same one will work for both rx and tx. */ + if(FXmacMsgBdRingClone(txringptr, &bdtemplate, FXMAC_MSG_SEND)) + { + return -EIO; + } + + /* init rx buffer */ + for (i = 0; i < dev_conf->rxbd_count; i++) + { + if(FXmacMsgBdRingAlloc(rxringptr, 1, &rxbd)) + { + LOG_ERR("InitDma: Error allocating RxBD\r\n"); + return -ERANGE; + } + + /* Enqueue to HW */ + if(FXmacMsgBdRingToHw(rxringptr, 1, rxbd)) + { + LOG_ERR("Error: committing RxBD to HW\r\n"); + FXmacMsgBdRingUnAlloc(rxringptr, 1, rxbd); + return -ERANGE; + } + + bdindex = FXMAC_MSG_BD_TO_INDEX(rxringptr, rxbd); + temp = (u32 *)rxbd; + *temp = 0; + if (bdindex == (dev_conf->rxbd_count - 1)) + { + *temp = XMAC_V2_RXDESC_WRAP; /* Marks last descriptor in receive buffer descriptor list */ + } + temp++; + *temp = 0; /* Clear word 1 in descriptor */ + + FXMAC_MSG_BD_SET_ADDRESS_RX(rxbd, (uintptr)(dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size) * bdindex)); + } + FXmacMsgSetQueuePtr(instance_p, instance_p->tx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_MSG_SEND); + FXmacMsgSetQueuePtr(instance_p, instance_p->rx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_MSG_RECV); + + return 0; +} + + + +static void eth_phytium_xmac_handle_tx_done(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + struct eth_phytium_xmac_v2_dev_cfg *dev_conf = (struct eth_phytium_xmac_v2_dev_cfg *)dev->config; + FXmacMsgCtrl *instance_p; + FXmacMsgBd *txbdset; + FXmacMsgBd *curbdpntr; + u32 n_bds; + FError status; + u32 n_pbufs_freed = 0; + u32 bdindex; + u32 *temp; + instance_p = &dev_data->instance; + FXmacMsgBdRing *txring; + + if (dev_conf->defer_txd_to_queue) + { + k_sem_take(&(dev_data->ring_sem), K_FOREVER); + } + txring = &(FXMAC_MSG_GET_TXRING((*instance_p))); + while (1) + { + /* obtain processed BD's */ + n_bds = FXmacMsgBdRingFromHwTx(txring, dev_conf->txbd_count, &txbdset); + if (n_bds == 0) + { + break; + } + /* free the processed BD's */ + n_pbufs_freed = n_bds; + curbdpntr = txbdset; + while (n_pbufs_freed > 0) + { + bdindex = FXMAC_MSG_BD_TO_INDEX(txring, curbdpntr); + temp = (u32 *)curbdpntr; + *temp = 0; /* Word 0 */ + temp++; + + if (bdindex == (dev_conf->txbd_count - 1)) + { + *temp = XMAC_V2_TXDESC_USED | XMAC_V2_TXDESC_WRAP; /* Word 1 ,used/Wrap – marks last descriptor in transmit buffer descriptor list.*/ + } + else + { + *temp = XMAC_V2_TXDESC_USED; /* Word 1 , Used – must be zero for GEM to read data to the transmit buffer.*/ + } + + curbdpntr = FXMAC_MSG_BD_RING_NEXT(txring, curbdpntr); + n_pbufs_freed--; + + } + + status = FXmacMsgBdRingFree(txring, n_bds, txbdset); + if (status != FT_SUCCESS) + { + LOG_ERR("Failure while freeing in Tx Done ISR\r\n"); + } + } + + if (dev_conf->defer_txd_to_queue) + { + k_sem_give(&(dev_data->ring_sem)); + } + + /* Re-enable the TX complete interrupt source */ + FXmacMsgEnableIrq(instance_p, 0, FXMAC_MSG_INT_TX_COMPLETE); + + /* Indicate completion to a blocking eth_xlnx_gem_send() call */ + k_sem_give(&dev_data->tx_done_sem); +} + +static void eth_phytium_xmac_tx_done_work(struct k_work *item) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = CONTAINER_OF(item, struct eth_phytium_xmac_v2_dev_data, tx_done_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_xmac_handle_tx_done(dev); +} + +/** + * @name: eth_phytium_xmac_v2_send + * @msg: Sends an Ethernet frame. The frame is contained in a packet that is managed by the networking stack. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @param {struct net_pkt} *pkt is a pointer to the network packet that contains the data to be sent. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_v2_send(const struct device *dev, struct net_pkt *pkt) +{ + struct eth_phytium_xmac_v2_dev_cfg *dev_conf = (struct eth_phytium_xmac_v2_dev_cfg *)dev->config; + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *instance_p; + + FXmacMsgBd *txbdset, *txbd, *last_txbd = NULL; + FXmacMsgBdRing *txring; + u32 bdindex; + + uint16_t tx_data_length; + uint16_t tx_data_remaining; + void *tx_buffer_offs; + uint32_t bds_reqd; + uint32_t tx_length = 0; + instance_p = &dev_data->instance; + txring = &FXMAC_MSG_GET_TXRING((*instance_p)); + + if (!dev_data->started || dev_data->eff_link_speed == LINK_DOWN || (!net_if_flag_is_set(dev_data->iface, NET_IF_UP))) + { +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + return -EIO; + } + + tx_data_length = tx_data_remaining = net_pkt_get_len(pkt); + if (tx_data_length == 0) + { + LOG_ERR("%s cannot TX, zero packet length", dev->name); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.errors.tx++; +#endif + return -EINVAL; + } + + bds_reqd = (uint8_t)((tx_data_length + (dev_conf->tx_buffer_size - 1)) / dev_conf->tx_buffer_size); + + if (dev_conf->defer_txd_to_queue) + { + k_sem_take(&(dev_data->ring_sem), K_FOREVER); + } + else + { + FXmacMsgDisableIrq(instance_p, 0, FXMAC_MSG_INT_TX_COMPLETE); + } + + /* obtain as many BD's */ + if(FXmacMsgBdRingAlloc(txring, bds_reqd, &txbdset)) + { + LOG_ERR("sgsend: Error allocating TxBD\r\n"); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.tx_dropped++; +#endif + FXmacMsgEnableIrq(instance_p, 0, FXMAC_MSG_INT_TX_COMPLETE); + return ERR_GENERAL; + } + + if (dev_conf->defer_txd_to_queue) + { + k_sem_give(&(dev_data->ring_sem)); + } + else + { + FXmacMsgEnableIrq(instance_p, 0, FXMAC_MSG_INT_TX_COMPLETE); + } + + /* + * Scatter the contents of the network packet's buffer to + * one or more DMA buffers. + */ + net_pkt_cursor_init(pkt); + txbd = txbdset; + while (tx_data_remaining) + { + bdindex = FXMAC_MSG_BD_TO_INDEX(txring, txbd); + + /* Calculate the base pointer of the target TX buffer */ + tx_buffer_offs = (void *)(dev_data->first_tx_buffer + (ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->tx_buffer_size) * bdindex)); + + /* Copy packet data to DMA buffer */ + tx_length = (tx_data_remaining < dev_conf->tx_buffer_size) ? tx_data_remaining : dev_conf->tx_buffer_size; + net_pkt_read(pkt, (void *)tx_buffer_offs, tx_length); + + FXMAC_MSG_BD_SET_ADDRESS_TX(txbd, (uintptr)tx_buffer_offs); + + FXMAC_MSG_BD_SET_LENGTH(txbd, tx_length & 0x3FFF); + + last_txbd = txbd; + FXMAC_MSG_BD_CLEAR_LAST(txbd); + txbd = FXMAC_MSG_BD_RING_NEXT(txring, txbd); + tx_data_remaining -= (tx_data_remaining < dev_conf->tx_buffer_size) ? tx_data_remaining : dev_conf->tx_buffer_size; + } + FXMAC_MSG_BD_SET_LAST(last_txbd); + + bdindex = FXMAC_MSG_BD_TO_INDEX(txring, txbd); + + FXMAC_MSG_BD_CLEAR_TX_USED(last_txbd); + + if(FXmacMsgBdRingToHw(txring, bds_reqd, txbdset)) + { + LOG_ERR("sgsend: Error submitting TxBD\r\n"); + } + + /* Start transmit */ + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_TX_PTR(0), bdindex); + +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.bytes.sent += tx_data_length; + dev_data->stats.pkts.tx++; +#endif + + return 0; +} + +static void eth_phytium_xmac_setup_rx_bds(const struct device *dev,FXmacMsgBdRing *rxring) +{ + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + FXmacMsgBd *rxbd; + FError status; + u32 freebds; + u32 bdindex; + u32 *temp; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + freebds = FXMAC_MSG_BD_RING_GET_FREE_CNT(rxring); + while (freebds > 0) + { + freebds--; + status = FXmacMsgBdRingAlloc(rxring, 1, &rxbd); + if (status != FT_SUCCESS) + { + LOG_ERR("SetupRxBds: Error allocating RxBD\r\n"); + return; + } + status = FXmacMsgBdRingToHw(rxring, 1, rxbd); + if (status != FT_SUCCESS) + { + LOG_ERR("Error committing RxBD to hardware: "); + if (status == FXMAC_MSG_ERR_SG_LIST) + { + LOG_ERR("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with FXmacMsgBdRingAlloc()\r\n"); + } + else + { + LOG_ERR("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"); + } + + FXmacMsgBdRingUnAlloc(rxring, 1, rxbd); + return; + } + + + bdindex = FXMAC_MSG_BD_TO_INDEX(rxring, rxbd); + temp = (u32 *)rxbd; + if (bdindex == (dev_conf->rxbd_count - 1)) + { + *temp = XMAC_V2_RXDESC_WRAP; /* Mask last descriptor in receive buffer list */ + } + else + { + *temp = 0; + } + temp++; + *temp = 0; + + FXMAC_MSG_BD_SET_ADDRESS_RX(rxbd, (uintptr)(dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size) * bdindex)); + } +} + +static void eth_phytium_xmac_handle_rx_pending(const struct device *dev) +{ + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + FXmacMsgBd *rxbdset, *curbdptr; + FXmacMsgBdRing *rxring; + volatile u32 bd_processed; + u32 k; + u32 bdindex; + FXmacMsgCtrl *instance_p; + struct net_pkt *pkt; + uint32_t rx_data_length; + instance_p = &dev_data->instance; + rxring = &FXMAC_MSG_GET_RXRING((*instance_p)); + + /* Re-enable the frame received interrupt source */ + FXmacMsgEnableIrq(instance_p, 0, FXMAC_MSG_INT_RX_COMPLETE); + + while (1) + { + bd_processed = FXmacMsgBdRingFromHwRx(rxring, dev_conf->rxbd_count, &rxbdset); + if (bd_processed <= 0) + { + break; + } + + for (k = 0, curbdptr = rxbdset; k < bd_processed; k++) + { + bdindex = FXMAC_MSG_BD_TO_INDEX(rxring, curbdptr); + rx_data_length = FXMAC_MSG_BD_GET_LENGTH(curbdptr); + if(rx_data_length > dev_conf->rx_buffer_size) + { + LOG_ERR("rx_data_length length is error: %u bytes \r\n", + rx_data_length); + goto error_exit; + } + + pkt = net_pkt_rx_alloc_with_buffer(dev_data->iface, rx_data_length, + AF_UNSPEC, 0, K_FOREVER); + if (pkt == NULL) + { + LOG_ERR("RX packet buffer alloc failed: %u bytes", + rx_data_length); +#ifdef CONFIG_NET_STATISTICS_ETHERNET + dev_data->stats.errors.rx++; + dev_data->stats.error_details.rx_no_buffer_count++; +#endif + /* free up the BD's */ + goto error_exit; + } + + net_pkt_write(pkt, (const void *) + (dev_data->first_rx_buffer_virt + ETH_ALIGNMENT_OFFSET_DEFINED(dev_conf->rx_buffer_size)*bdindex), + rx_data_length); + + if (net_recv_data(dev_data->iface, pkt) < 0) { + printf("%s RX packet hand-over to IP stack failed", dev->name); + net_pkt_unref(pkt); + } +#ifdef CONFIG_NET_STATISTICS_ETHERNET + else { + dev_data->stats.bytes.received += rx_data_length; + dev_data->stats.pkts.rx++; + } +#endif + curbdptr = FXMAC_MSG_BD_RING_NEXT(rxring, curbdptr); + } + FXmacMsgBdRingFree(rxring, bd_processed, rxbdset); + eth_phytium_xmac_setup_rx_bds(dev,rxring); + } + + return; + +error_exit: + printf("eth_phytium_xmac_handle_rx_pending error exit \r\n"); + FXmacMsgBdRingFree(rxring, bd_processed, rxbdset); +} + +static void eth_phytium_xmac_rx_pending_work(struct k_work *item) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = CONTAINER_OF(item, + struct eth_phytium_xmac_v2_dev_data, rx_pend_work); + const struct device *dev = net_if_get_device(dev_data->iface); + + eth_phytium_xmac_handle_rx_pending(dev); +} + + +static void FXmacMsgSendHandler(void *arg) +{ + const struct device *dev = (const struct device *)arg; + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + FXmacMsgDisableIrq(instance_p, 0, FXMAC_MSG_INT_TX_COMPLETE); + + if (dev_conf->defer_txd_to_queue) + { + k_work_submit(&dev_data->tx_done_work); + } + else + { + eth_phytium_xmac_handle_tx_done(dev); + } +} + +static void FXmacMsgRecvHandler(void *arg) +{ + const struct device *dev = (const struct device *)arg; + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + FXmacMsgDisableIrq(instance_p, 0, FXMAC_MSG_INT_RX_COMPLETE); + + if (dev_conf->defer_rxp_to_queue) + { + k_work_submit(&dev_data->rx_pend_work); + } + else + { + printk("recv data \r\n"); + eth_phytium_xmac_handle_rx_pending(dev); + printk("recv data exit \r\n"); + } +} + +#ifdef CONFIG_NET_STATISTICS_ETHERNET +/** + * @name: eth_phytium_xmac_v2_stats + * @msg: Retrieves the Ethernet statistics for the device. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {struct net_stats_eth} * A pointer to the statistics structure. + */ +static struct net_stats_eth *eth_phytium_xmac_v2_stats(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + + return &dev_data->stats; +} +#endif + +/** + * @name: FXmacMsgSetupIsr + * @msg: Sets up the interrupt service routine handlers for transmit, receive, and error events. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + */ +static void FXmacMsgSetupIsr(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + /* Setup callbacks */ + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + FXmacMsgSetHandler(instance_p, FXMAC_MSG_HANDLER_DMASEND, FXmacMsgSendHandler, (void *)dev); + FXmacMsgSetHandler(instance_p, FXMAC_MSG_HANDLER_DMARECV, FXmacMsgRecvHandler,(void *) (void *)dev); +} + +/** + * @name: eth_phytium_xmac_v2_start_device + * @msg: Starts the Ethernet device, enabling packet transmission and reception. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_v2_start_device(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + /* Setup callbacks */ + if (dev_data->started) + { + return 0; + } + dev_data->started = true; + + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + FXmacMsgStart(instance_p); + return 0; +} + +/** + * @name: eth_phytium_xmac_v2_stop_device + * @msg: Stops the Ethernet device, disabling packet transmission and reception. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_v2_stop_device(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + if (!dev_data->started) + { + return 0; + } + dev_data->started = false; + + /* Cancel the delayed work that polls the link state */ + if (k_work_delayable_remaining_get(&dev_data->phy_poll_delayed_work) != 0) + { + k_work_cancel_delayable(&dev_data->phy_poll_delayed_work); + } + + FXmacMsgStop(instance_p); + + return 0; +} + +/** + * @name: eth_phytium_xmac_v2_isr + * @msg: Interrupt service routine for handling all interrupts from the Ethernet device. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + */ +static void eth_phytium_xmac_v2_isr(const struct device *dev) +{ + u32 reg_isr; + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + FXmacMsgCtrl *instance_p; + instance_p = &dev_data->instance; + + reg_isr = FXMAC_MSG_READ(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index)); + /* 发送中断 */ + { + /* 发送完成中断 */ + if ((reg_isr & BIT(FXMAC_MSG_TXCOMP_INDEX)) != 0x00000000U) + { + if (instance_p->send_irq_handler) + { + instance_p->send_irq_handler(instance_p->send_args); + } + + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), BIT(FXMAC_MSG_TXCOMP_INDEX)); + } + } + + /* 发送错误中断 */ + if (((reg_isr & (BIT(FXMAC_MSG_DMA_ERR_INDEX) | BIT(FXMAC_MSG_RETRY_LIMIT_INDEX) | BIT(FXMAC_MSG_TX_UNDER_RUN_INDEX))) != 0x00000000U) && (!(reg_isr & BIT(FXMAC_MSG_TXCOMP_INDEX)) != 0x00000000U)) + { + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), (BIT(FXMAC_MSG_DMA_ERR_INDEX) | BIT(FXMAC_MSG_RETRY_LIMIT_INDEX) | BIT(FXMAC_MSG_TX_UNDER_RUN_INDEX))); + } + } + } + + /* 接收中断 */ + { + /* 接收完成中断 */ + if ((reg_isr & BIT(FXMAC_MSG_RXCOMP_INDEX)) != 0x00000000U) + { + if (instance_p->recv_irq_handler) + { + instance_p->recv_irq_handler(instance_p->recv_args); + } + + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), BIT(FXMAC_MSG_RXCOMP_INDEX)); + } + } + + /* 接收错误中断 */ + if ((reg_isr & (BIT(FXMAC_MSG_RUSED_INDEX) | BIT(FXMAC_MSG_RXOVERRUN_INDEX) | BIT(FXMAC_MSG_RESP_ERR_INDEX))) != 0x00000000U) + { + if ((reg_isr & BIT(FXMAC_MSG_RUSED_INDEX)) != 0x00000000U) + { + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), BIT(FXMAC_MSG_RUSED_INDEX)); + } + } + + if ((reg_isr & BIT(FXMAC_MSG_RXOVERRUN_INDEX)) != 0x00000000U) + { + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), BIT(FXMAC_MSG_RXOVERRUN_INDEX)); + } + } + + if ((reg_isr & BIT(FXMAC_MSG_RESP_ERR_INDEX)) != 0x00000000U) + { + if(instance_p->caps & FXMAC_MSG_CAPS_ISR_CLEAR_ON_WRITE) + { + FXMAC_MSG_WRITE(instance_p, FXMAC_MSG_INT_SR(instance_p->queues[0].index), BIT(FXMAC_MSG_RESP_ERR_INDEX)); + } + } + } + } +} + +/** + * @name: eth_phytium_xmac_v2_iface_init + * @msg: Initializes the network interface for the Ethernet driver. Sets the link address and registers the Ethernet interface with the network stack. + * @param {struct net_if} *iface is a pointer to the network interface structure. + */ +static void eth_phytium_xmac_v2_iface_init(struct net_if *iface) +{ + const struct device *dev = net_if_get_device(iface); + const struct eth_phytium_xmac_v2_dev_cfg *dev_conf = dev->config; + struct eth_phytium_xmac_v2_dev_data *dev_data = dev->data; + + /* Set the initial contents of the current instance's run-time data */ + dev_data->iface = iface; + net_if_set_link_addr(iface, dev_data->mac_addr, 6, NET_LINK_ETHERNET); + ethernet_init(iface); + net_if_carrier_off(iface); + + /* + * Initialize the (delayed) work items for RX pending, TX done + * and PHY status polling handlers + */ + k_work_init(&dev_data->tx_done_work, eth_phytium_xmac_tx_done_work); + k_work_init(&dev_data->rx_pend_work, eth_phytium_xmac_rx_pending_work); + k_work_init_delayable(&dev_data->phy_poll_delayed_work, eth_phytium_xmac_v2_poll_phy); + + /* Initialize TX completion semaphore */ + k_sem_init(&dev_data->tx_done_sem, 0, 1); + + /* + * Initialize semaphores in the RX/TX BD rings which have not + * yet been initialized + */ + k_sem_init(&dev_data->ring_sem, 1, 1); + /* RX BD ring semaphore is not required at the time being */ + + /* Initialize the device's interrupt */ + dev_conf->config_func(dev); + + /* Submit initial PHY status polling delayed work */ + k_work_reschedule(&dev_data->phy_poll_delayed_work, K_NO_WAIT); +} + +/* 设置特性 */ +void FXmacMsgFeatureSetOptions(u32 feature, FXmacMsgCtrl* xmac_p) +{ + u16 cmd_id, cmd_subid; + cmd_id = FXMAC_MSG_CMD_SET; + + /* 巨帧 */ + if (feature & FXMAC_MSG_LWIP_PORT_CONFIG_JUMBO) + { + xmac_p->config.network_default_config |= FXMAC_MSG_JUMBO_ENABLE_OPTION; + xmac_p->rx_buffer_len = FXMAC_MSG_MAX_FRAME_SIZE_JUMBO; + LOG_INF("FXMAC_MSG_JUMBO_ENABLE_OPTION is ok"); + } + + /* 单播 */ + if (feature & FXMAC_MSG_LWIP_PORT_CONFIG_UNICAST_ADDRESS_FILITER) + { + LOG_INF("FXMAC_MSG_UNICAST_OPTION is ok"); + } + + /* 多播 */ + if (feature & FXMAC_MSG_LWIP_PORT_CONFIG_MULTICAST_ADDRESS_FILITER) + { + cmd_subid = FXMAC_MSG_CMD_SET_ENABLE_MC; + FXmacMsgSendMessage(xmac_p, cmd_id, cmd_subid, NULL, 0, 1); + LOG_INF("FXMAC_MSG_MULTICAST_OPTION is ok"); + } + + /* 全帧 */ + if (feature & FXMAC_MSG_LWIP_PORT_CONFIG_COPY_ALL_FRAMES) + { + cmd_subid = FXMAC_MSG_CMD_SET_ENABLE_PROMISE; + FXmacMsgSendMessage(xmac_p, cmd_id, cmd_subid, NULL, 0, 0); + LOG_INF("FXMAC_MSG_PROMISC_OPTION is ok"); + } + + /* 关闭FCS(帧校验序列)校验 */ + if (feature & FXMAC_MSG_LWIP_PORT_CONFIG_CLOSE_FCS_CHECK) + { + LOG_INF("FXMAC_MSG_FCS_STRIP_OPTION is ok"); + } +} + +/** + * @name: eth_phytium_xmac_v2_dev_init + * @msg: Initializes the Ethernet device, including hardware configuration and MAC address setting. + * @param {const struct device} *dev is a pointer to the device structure for the driver instance. + * @return {int} Zero on success or negative error code on failure. + */ +static int eth_phytium_xmac_v2_dev_init(const struct device *dev) +{ + struct eth_phytium_xmac_v2_dev_data *dev_data = (struct eth_phytium_xmac_v2_dev_data *)dev->data; + struct eth_phytium_xmac_v2_dev_cfg *dev_conf = (struct eth_phytium_xmac_v2_dev_cfg *)dev->config; + FXmacMsgConfig mac_config; + FXmacMsgCtrl *instance_p; + uint32_t xmac_options; + int ret; + + /* DT */ + uintptr_t mac_base = DT_INST_PROP_BY_IDX(0, mac_regs, 1); + size_t mac_size = DT_INST_PROP_BY_IDX(0, mac_regs, 3); + + uintptr_t msg_base = DT_INST_PROP_BY_IDX(0, msg_regs, 1); + size_t msg_size = DT_INST_PROP_BY_IDX(0, msg_regs, 3); + + /* init base */ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + + /* config init */ + mac_config.instance_id = 0; + + /* 获取配置 */ + mac_config = *FXmacMsgLookupConfig(mac_config.instance_id); + + /* 用户设置 */ + ret = eth_phytium_xmac_config_convert(dev_conf, &mac_config, &xmac_options); + if(ret) + { + return -EINVAL; + } + + /* regfile地址映射 */ + mm_reg_t regfile_virt_addr; + device_map(®file_virt_addr, mac_base, mac_size, K_MEM_CACHE_NONE); + mac_config.msg.regfile = regfile_virt_addr; + + /* shmem地址映射 */ + mm_reg_t shmem_virt_addr; + device_map(&shmem_virt_addr, msg_base, msg_size, K_MEM_CACHE_NONE); + mac_config.msg.shmem = shmem_virt_addr; + + instance_p = &dev_data->instance; + if(FXmacMsgCfgInitialize(instance_p, &mac_config)) + { + return -EIO; + } + + /* 初始化MSG消息队列 */ + FXmacMsgInitRing(instance_p); + + /* 获取配置参数 */ + FXmacMsgGetFeatureAll(instance_p); + + /* 硬件重置 */ + FXmacMsgResetHw(instance_p); + + /* 设置特性 */ + FXmacMsgFeatureSetOptions(xmac_options, instance_p); + + /* 初始化硬件 */ + FXmacMsgInitHw(instance_p, (void *)(dev_data->mac_addr)); + + /* 初始化PHY */ + if(mac_config.interface != FXMAC_MSG_PHY_INTERFACE_MODE_USXGMII) + { + if(FXmacMsgPhyInit(instance_p, instance_p->config.speed, instance_p->config.duplex, instance_p->config.auto_neg, FXMAC_MSG_PHY_RESET_ENABLE)) + { + LOG_WRN("FXmacMsgPhyInit is error \r\n"); + } + } + + /* 初始化PHY接口 */ + FXmacMsgInterfaceConfig(instance_p, 0); + + /* 初始化DMA描述符 */ + eth_phytium_xmac_v2_init_dma(dev); + + /* 初始化中断 */ + instance_p->mask = ((u32)BIT(FXMAC_MSG_DMA_ERR_INDEX) | (u32)BIT(FXMAC_MSG_RETRY_LIMIT_INDEX) | (u32)BIT(FXMAC_MSG_TX_UNDER_RUN_INDEX) + | (u32)BIT(FXMAC_MSG_RXOVERRUN_INDEX) | BIT(FXMAC_MSG_RESP_ERR_INDEX) | BIT(FXMAC_MSG_RUSED_INDEX) + | (u32)BIT(FXMAC_MSG_RXCOMP_INDEX) | (u32)BIT(FXMAC_MSG_TXCOMP_INDEX)); + FXmacMsgSetupIsr(dev); + + return 0; +} diff --git a/drivers/ethernet/eth_phytium_xmac_v2.h b/drivers/ethernet/eth_phytium_xmac_v2.h new file mode 100644 index 0000000000000000000000000000000000000000..5090dac605879fb6abdd4a1ccfe563564fd1e3b3 --- /dev/null +++ b/drivers/ethernet/eth_phytium_xmac_v2.h @@ -0,0 +1,163 @@ +#ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_XMAC_V2_H_ +#define _ZEPHYR_DRIVERS_ETHERNET_ETH_PHYTIUM_XMAC_V2_H_ + +#include "fxmac_msg_bd.h" + +/* Tx Desc Word1 */ +#define XMAC_V2_TXDESC_USED (1 << 31) /* done txmitting */ +#define XMAC_V2_TXDESC_WRAP (1 << 30) /* end descr ring */ +#define XMAC_V2_TXDESC_RETRY_ERR (1 << 29) +#define XMAC_V2_TXDESC_UNDER_RUN (1 << 28) /* underrun error */ +#define XMAC_V2_TXDESC_AHB_ERR (1 << 27) +#define XMAC_V2_TXDESC_LATE_COLL (1 << 26) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_MASK (7 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_VLAN_HDR_ERR (1 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_SNAP_HDR_ERR (2 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_IP_HDR_ERR (3 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_UNKNOWN_TYPE (4 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_UNSUPP_FRAG (5 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_NOT_TCPUDP (6 << 20) +#define XMAC_V2_TXDESC_CKSUM_GEN_STAT_SHORT_PKT (7 << 20) +#define XMAC_V2_TXDESC_NO_CRC_APPENDED (1 << 16) +#define XMAC_V2_TXDESC_LAST_BUF (1 << 15) /* last in frame */ +#define XMAC_V2_TXDESC_LENGTH_MASK 0x3fff + +/* Rx Desc Word0 */ +#define XMAC_V2_RXDESC_WRAP (1 << 1) /* end descr ring */ +#define XMAC_V2_RXDESC_OWN (1 << 0) /* ownership flag */ +/* Rx Desc Word1 */ +#define XMAC_V2_RXDESC_BCAST (1 << 31) /* all 1's bcast */ +#define XMAC_V2_RXDESC_MULTI_MATCH (1 << 30) /* mutlicast match */ +#define XMAC_V2_RXDESC_UNICAST_MATCH (1 << 29) +#define XMAC_V2_RXDESC_EXTERNAL_MATCH (1 << 28) /* ext addr match */ +#define XMAC_V2_RXDESC_SPEC_MATCH_SHIFT 25 +#define XMAC_V2_RXDESC_SPEC_MATCH_MASK (3 << 25) +#define XMAC_V2_RXDESC_TYPE_ID_MATCH_SHIFT 22 +#define XMAC_V2_RXDESC_TYPE_ID_MATCH_MASK (3 << 22) +#define XMAC_V2_RXDESC_CKSUM_STAT_MASK (3 << 22) /* same as above */ +#define XMAC_V2_RXDESC_CKSUM_STAT_NONE (0 << 22) +#define XMAC_V2_RXDESC_CKSUM_STAT_IP_GOOD (1 << 22) +#define XMAC_V2_RXDESC_CKSUM_STAT_TCP_GOOD (2 << 22) /* and ip good */ +#define XMAC_V2_RXDESC_CKSUM_STAT_UDP_GOOD (3 << 22) /* and ip good */ +#define XMAC_V2_RXDESC_VLAN_DETECTED (1 << 21) +#define XMAC_V2_RXDESC_PRIO_DETECTED (1 << 20) +#define XMAC_V2_RXDESC_VLAN_PRIO_SHIFT 17 +#define XMAC_V2_RXDESC_VLAN_PRIO_MASK (7 << 17) +#define XMAC_V2_RXDESC_CFI (1 << 16) +#define XMAC_V2_RXDESC_EOF (1 << 15) /* end of frame */ +#define XMAC_V2_RXDESC_SOF (1 << 14) /* start of frame */ +#define XMAC_V2_RXDESC_BAD_FCS (1 << 13) +#define XMAC_V2_RXDESC_LENGTH_MASK 0x1fff + +/* DMA memory area instantiation macro */ +#define ETH_PHYTIUM_XMAC_V2_DMA_AREA_INST(port) \ +static struct eth_phytium_dma_area_gem##port eth_phytium_xmac_v2_##port##_dma_area\ + __aligned(4096); + +/* DMA memory area declaration macro */ +#define ETH_PHYTIUM_XMAC_V2_DMA_AREA_DECL(port) \ +struct eth_phytium_dma_area_gem##port {\ + uint8_t rx_bd[DT_INST_PROP(port, rx_buffer_descriptors) * (u32)sizeof(FXmacMsgBd)] __attribute__((aligned(256))) ;\ + uint8_t tx_bd[DT_INST_PROP(port, tx_buffer_descriptors) * (u32)sizeof(FXmacMsgBd)] __attribute__((aligned(256)));\ + uint8_t rx_buffer\ + [DT_INST_PROP(port, rx_buffer_descriptors)]\ + [((DT_INST_PROP(port, rx_buffer_size)\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))];\ + uint8_t tx_buffer\ + [DT_INST_PROP(port, tx_buffer_descriptors)]\ + [((DT_INST_PROP(port, tx_buffer_size)\ + + (ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))\ + & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT - 1))];\ +}; + + +/* RX/TX BD Ring initialization macro */ +#define ETH_PHYTIUM_XMAC_V2_INIT_BD_RING(port) \ + dev_data->rx_bdspace = &(eth_phytium_xmac_v2_##port##_dma_area.rx_bd[0]);\ + dev_data->tx_bdspace = &(eth_phytium_xmac_v2_##port##_dma_area.tx_bd[0]);\ + dev_data->first_rx_buffer = (uint8_t *)eth_phytium_xmac_v2_##port##_dma_area.rx_buffer;\ + dev_data->first_rx_buffer_virt = dev_data->first_rx_buffer ;\ + dev_data->first_tx_buffer = (uint8_t *)eth_phytium_xmac_v2_##port##_dma_area.tx_buffer; \ + dev_data->first_tx_buffer_virt =dev_data->first_tx_buffer ; + + + + +#define ETH_PHYTIUM_XMAC_V2_NET_DEV_INIT(port) \ +ETH_NET_DEVICE_DT_INST_DEFINE(port,\ + eth_phytium_xmac_v2_dev_init,\ + NULL,\ + ð_phytium_xmac_v2_##port##_dev_data,\ + ð_phytium_xmac_v2_##port##_dev_cfg,\ + CONFIG_ETH_INIT_PRIORITY,\ + ð_phytium_xmac_v2_apis,\ + NET_ETH_MTU); + + + +/* Device configuration data declaration macro */ +#define ETH_PHYTIUM_XMAC_V2_DEV_CONFIG(port) \ +static const struct eth_phytium_xmac_v2_dev_cfg eth_phytium_xmac_v2_##port##_dev_cfg = {\ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)), \ + .instance_id = port, \ + .config_func = eth_phytium_xmac_v2_##port##_irq_config,\ + .pll_clock_frequency = DT_INST_PROP(port, clock_frequency),\ + .phy_poll_interval = DT_INST_PROP(port, phy_poll_interval),\ + .defer_rxp_to_queue = !DT_INST_PROP(port, handle_rx_in_isr),\ + .defer_txd_to_queue = DT_INST_PROP(port, handle_tx_in_workq),\ + .rxbd_count = (uint8_t)\ + (DT_INST_PROP(port, rx_buffer_descriptors)),\ + .txbd_count = (uint8_t)\ + (DT_INST_PROP(port, tx_buffer_descriptors)),\ + .rx_buffer_size = (((uint16_t)(DT_INST_PROP(port, rx_buffer_size)) +\ + (ETH_PHYTIUM_BUFFER_ALIGNMENT-1)) & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT-1)),\ + .tx_buffer_size = (((uint16_t)(DT_INST_PROP(port, tx_buffer_size)) +\ + (ETH_PHYTIUM_BUFFER_ALIGNMENT-1)) & ~(ETH_PHYTIUM_BUFFER_ALIGNMENT-1)),\ + .phy_speed = DT_INST_PROP(port, phy_speed),\ + .interface_mode = DT_INST_PROP(port, interface_mode),\ + .dma_brust_length = DT_INST_PROP(port, dma_brust_length),\ + .max_queue_num = DT_INST_PROP(port, max_queue_num),\ + .phy_autonegotiation = DT_INST_PROP(port, phy_autonegotiation),\ + .enable_fdx = DT_INST_PROP(port, enable_fdx),\ + .enable_jumbo = DT_INST_PROP(port, enable_jumbo),\ + .enable_ucast_hash = DT_INST_PROP(port, enable_ucast_hash),\ + .copy_all_frames = DT_INST_PROP(port, copy_all_frames),\ + .disable_reject_fcs_crc_errors = DT_INST_PROP(port, disable_reject_fcs_crc_errors),\ + .enable_mcast_hash = DT_INST_PROP(port, enable_mcast_hash),\ +}; + +/* Device run-time data declaration macro */ +#define ETH_PHYTIUM_XMAC_V2_DEV_DATA(port) \ +static struct eth_phytium_xmac_v2_dev_data eth_phytium_xmac_v2_##port##_dev_data = {\ + .mac_addr = DT_INST_PROP(port, local_mac_address),\ + .started = 0,\ + .eff_link_speed = LINK_DOWN,\ + .phy_addr = 0,\ + .phy_id = 0,\ + .first_rx_buffer = NULL,\ + .first_tx_buffer = NULL\ +}; + +/* Interrupt configuration function macro */ +#define ETH_PHYTIUM_XMAC_V2_CONFIG_IRQ_FUNC(port) \ +static void eth_phytium_xmac_v2_##port##_irq_config(const struct device *dev)\ +{\ + ARG_UNUSED(dev);\ + IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority),\ + eth_phytium_xmac_v2_isr, DEVICE_DT_INST_GET(port), 0);\ + irq_enable(DT_INST_IRQN(port));\ +} + + +/* Top-level device initialization macro - bundles all of the above */ +#define ETH_PHYTIUM_XMAC_V2_INITIALIZE(port) \ +ETH_PHYTIUM_XMAC_V2_CONFIG_IRQ_FUNC(port);\ +ETH_PHYTIUM_XMAC_V2_DEV_CONFIG(port);\ +ETH_PHYTIUM_XMAC_V2_DEV_DATA(port);\ +ETH_PHYTIUM_XMAC_V2_DMA_AREA_DECL(port);\ +ETH_PHYTIUM_XMAC_V2_DMA_AREA_INST(port);\ +ETH_PHYTIUM_XMAC_V2_NET_DEV_INIT(port);\ + + +#endif diff --git a/drivers/interrupt_controller/intc_gicv3.c b/drivers/interrupt_controller/intc_gicv3.c index e3c25c4d8b8fcc7ef902fd8e3fc974813f28f153..09a2f75280db663b6509b65a71cfdbed88448ebc 100644 --- a/drivers/interrupt_controller/intc_gicv3.c +++ b/drivers/interrupt_controller/intc_gicv3.c @@ -405,6 +405,9 @@ static void gicv3_cpuif_init(void) /* Configure PPIs as level triggered */ sys_write32(0, ICFGR(base, 1)); + + +#ifndef CONFIG_USE_EL2 /* * Check if system interface can be enabled. * 'icc_sre_el3' needs to be configured at 'EL3' @@ -421,6 +424,26 @@ static void gicv3_cpuif_init(void) __ASSERT_NO_MSG(icc_sre & ICC_SRE_ELx_SRE_BIT); } +#else + /* + * Check if system interface can be enabled. + * 'icc_sre_el3' needs to be configured at 'EL3' + * to allow access to 'icc_sre_el1' at 'EL1' + * eg: z_arch_el3_plat_init can be used by platform. + */ + icc_sre = read_sysreg(ICC_SRE_EL2); + + if (!(icc_sre & ICC_SRE_ELx_SRE_BIT)) { + icc_sre = (icc_sre | ICC_SRE_ELx_SRE_BIT | + ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT); + write_sysreg(icc_sre, ICC_SRE_EL2); + icc_sre = read_sysreg(ICC_SRE_EL2); + + __ASSERT_NO_MSG(icc_sre & ICC_SRE_ELx_SRE_BIT); + } + +#endif + write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1); diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 1dce91d59778661f3cacfbb369a4cef695a718d5..6ab336dadb09b96c2aa933350063df91551117a9 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -38,5 +38,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCI_IO_MUX pinctrl_mci_io_mux.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_ENE_KB1200 pinctrl_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_PHYTIUM pinctrl_phytium.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b919fa0f169b0009d67e6b3fc24af89de8ed829f..bb8d4283881e86d3664f956fbdfbaaf3cebe5423 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -66,6 +66,7 @@ source "drivers/pinctrl/Kconfig.mci_io_mux" source "drivers/pinctrl/Kconfig.ene" source "drivers/pinctrl/Kconfig.zynqmp" source "drivers/pinctrl/Kconfig.max32" +source "drivers/pinctrl/Kconfig.phytium" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.phytium b/drivers/pinctrl/Kconfig.phytium new file mode 100644 index 0000000000000000000000000000000000000000..e0c80c267d120028668f5231085270494c9dacba --- /dev/null +++ b/drivers/pinctrl/Kconfig.phytium @@ -0,0 +1,22 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config PINCTRL_PHYTIUM + bool "Pin controller driver for phytium" + default n + depends on DT_HAS_PHYTIUM_PINCTRL_ENABLED + + help + Enable pin controller driver for phytium . \ No newline at end of file diff --git a/drivers/pinctrl/pinctrl_phytium.c b/drivers/pinctrl/pinctrl_phytium.c new file mode 100644 index 0000000000000000000000000000000000000000..e80da694d4bb412130d395ccb37db8e08a55cfbb --- /dev/null +++ b/drivers/pinctrl/pinctrl_phytium.c @@ -0,0 +1,99 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DT_DRV_COMPAT phytium_pinctrl +LOG_MODULE_REGISTER(pinctrl, CONFIG_PINCTRL_LOG_LEVEL); + +FIOPadCtrl iopad_ctrl; + +static FError pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) +{ + FError ret; + ret = FIOPadSetFunc(&iopad_ctrl, pin->pin_reg_offset, pin->func_num); + if (ret != FIOPAD_SUCCESS) + { + LOG_ERR("FIOPadSetFunc error."); + } + + return ret; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + FError ret; + ARG_UNUSED(reg); + for (uint8_t i = 0U; i < pin_cnt; i++) + { + ret = pinctrl_configure_pin(pins++); + if (ret != FIOPAD_SUCCESS) + { + LOG_ERR("pinctrl_configure_pin error."); + } + } + return 0; +} + +struct pinctrl_config { + DEVICE_MMIO_ROM; +}; + +struct pinctrl_data { + DEVICE_MMIO_RAM; +}; + +static int phytium_pinctrl_init(const struct device *dev) +{ + FIOPadConfig config_p; + config_p.instance_id = 0; + + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + FIOPadCfgInitialize(&iopad_ctrl, &config_p); + + iopad_ctrl.config.base_address = DEVICE_MMIO_GET(dev); + + return 0; +} + +#define PHYTIUM_PINCTRL_INIT(n) \ + static const struct pinctrl_config pinctrl_##n##_config = { \ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ + }; \ + \ + static struct pinctrl_data pinctrl_##n##_data = { \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, \ + &phytium_pinctrl_init, \ + NULL, \ + &pinctrl_##n##_data, \ + &pinctrl_##n##_config, \ + PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(PHYTIUM_PINCTRL_INIT) + diff --git a/drivers/sdhc/CMakeLists.txt b/drivers/sdhc/CMakeLists.txt index 42985f873f1f08224cf44a7ab6b4975a8985822c..f88a5e47e836085926e6dd4d8588b3c86a4e186d 100644 --- a/drivers/sdhc/CMakeLists.txt +++ b/drivers/sdhc/CMakeLists.txt @@ -12,4 +12,5 @@ zephyr_library_sources_ifdef(CONFIG_INTEL_EMMC_HOST intel_emmc_host.c) zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c) zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c) zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c) +zephyr_library_sources_ifdef(CONFIG_PHYTIUM_USDHC phytium_sdhc.c) endif() diff --git a/drivers/sdhc/Kconfig b/drivers/sdhc/Kconfig index b6b1276207b955e03221117c675dbd4c5aa7fd86..26b750540091f150eea8379d21e543e6b1dc2b11 100644 --- a/drivers/sdhc/Kconfig +++ b/drivers/sdhc/Kconfig @@ -17,6 +17,7 @@ source "drivers/sdhc/Kconfig.sam_hsmci" source "drivers/sdhc/Kconfig.intel" source "drivers/sdhc/Kconfig.sdhc_cdns" source "drivers/sdhc/Kconfig.esp32" +source "drivers/sdhc/Kconfig.phytium_sdhc" config SDHC_INIT_PRIORITY int "SDHC driver init priority" diff --git a/drivers/sdhc/Kconfig.phytium_sdhc b/drivers/sdhc/Kconfig.phytium_sdhc new file mode 100644 index 0000000000000000000000000000000000000000..9018be571cc7adc8cc84094e573038ddc517152c --- /dev/null +++ b/drivers/sdhc/Kconfig.phytium_sdhc @@ -0,0 +1,49 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config PHYTIUM_USDHC + bool "PHYTIUM SDHC Driver" + default y + depends on DT_HAS_PHYTIUM_SDHC_ENABLED + select SDHC_SUPPORTS_NATIVE_MODE + select EVENTS + select PHYTIUM_PINCTRL + help + Enable the PHYTIUM SD Host controller driver + + +if PHYTIUM_USDHC + +config PHYTIUM_USDHC_DMA_SUPPORT + bool "DMA support for USDHC" + default y + select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT + help + Enable DMA support for USDHC + +config PHYTIUM_PINCTRL + bool + +# SDIF DMA needs 32 bit aligned buffers +config SDHC_BUFFER_ALIGNMENT + int "Size of DMA descriptor buffer in bytes" + default 512 + +config PHYTIUM_SDIF_DMA_DESC_LENGTH + int "Length of DMA descriptor length" + default 256 + help + Size of PHYTIUM SDIF DMA descriptor length +endif \ No newline at end of file diff --git a/drivers/sdhc/phytium_sdhc.c b/drivers/sdhc/phytium_sdhc.c new file mode 100644 index 0000000000000000000000000000000000000000..52dd3a4387de4d79628e39b2cced2c43232d15e7 --- /dev/null +++ b/drivers/sdhc/phytium_sdhc.c @@ -0,0 +1,757 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#define DT_DRV_COMPAT phytium_sdhc + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +static void card_stoptrans(const struct device *dev) ; + +static int card_setblcok(const struct device *dev, uint32_t num_blocks) ; + + +LOG_MODULE_REGISTER(sdhc, CONFIG_SDHC_LOG_LEVEL); + +#define FSDIF_IRQ_BIT_CMD_DONE 1 +#define FSDIF_IRQ_BIT_DATA_DONE 2 +#define FSDIF_IRQ_BIT_ERROR_OCCUR 4 +#define FSDIF_IRQ_CMD_BIT_MASK (FSDIF_IRQ_BIT_CMD_DONE|FSDIF_IRQ_BIT_ERROR_OCCUR) +#define FSDIF_IRQ_DATA_BIT_MASK (FSDIF_IRQ_BIT_CMD_DONE|FSDIF_IRQ_BIT_DATA_DONE|FSDIF_IRQ_BIT_ERROR_OCCUR) + +struct usdhc_config { + DEVICE_MMIO_ROM; + + uint32_t pio_id ; + uint32_t pio_base ; + uint32_t pio_length; + uint32_t instance_id ; + uint32_t is_enable_irq ; + + bool no_180_vol; + bool mmc_hs200_1_8v; + bool mmc_hs400_1_8v; + bool non_removeable; + uint32_t max_bus_freq; + uint32_t min_bus_freq; + void (*irq_config_func)(const struct device *dev); +}; + +struct usdhc_data { + DEVICE_MMIO_RAM; + struct sdhc_host_props props; + struct sdhc_io cur_ios; + bool card_present; + struct sdhc_io host_io; + struct k_mutex access_mutex; +#if CONFIG_PHYTIUM_USDHC_DMA_SUPPORT + FSdifIDmaDesc *usdhc_dma_descriptor; /* ADMA descriptor table (noncachable) */ + uint32_t dma_descriptor_len; /* DMA descriptor table length in words */ +#endif + /* pin ctrl */ + FIOPadCtrl iopad_ctrl; + FSdif instance ; + FSdifCmdData cmd_data ; + FSdifData trans_data ; + struct k_event irq_event; /* include err、cmd、data event */ + +}; + +static int card_polling_busy(const struct device *dev, int timeout_us); + +/* irq test */ +static void phytium_sdhc_card_detect_handler(FSdif *const instance_p, void *args, u32 status, u32 dmac_status) +{ + (void)instance_p; + (void)status; + (void)dmac_status; + LOG_DBG("Card detected !!!"); +} + +static void phytium_sdhc_command_done_handler(FSdif *const instance_p, void *args, u32 status, u32 dmac_status) +{ + struct usdhc_data *data = (struct usdhc_data *)args; + (void)instance_p; + (void)status; + (void)dmac_status; + /*Replace cmd_done by event */ + k_event_post(&data->irq_event,FSDIF_IRQ_BIT_CMD_DONE) ; +} + +static void phytium_sdhc_data_done_handler(FSdif *const instance_p, void *args, u32 status, u32 dmac_status) +{ + struct usdhc_data *data = (struct usdhc_data *)args; + + uint32_t check_status = status & (FSDIF_INT_DTO_BIT | FSDIF_INT_RCRC_BIT | + FSDIF_INT_DCRC_BIT | FSDIF_INT_RE_BIT | + FSDIF_INT_DRTO_BIT | FSDIF_INT_EBE_BIT | + FSDIF_INT_SBE_BCI_BIT | FSDIF_INT_RTO_BIT); + uint32_t check_dmac = dmac_status & (FSDIF_DMAC_STATUS_AIS | FSDIF_DMAC_STATUS_DU); + + if (check_status | check_dmac) + { + if (check_status & FSDIF_INT_DTO_BIT) + { + /* Replace data_done by event */ + k_event_post(&data->irq_event,FSDIF_IRQ_BIT_DATA_DONE) ; + } + else + { + LOG_DBG("Xfer data error, status: 0x%x, dmac status: 0x%x", + check_status, check_dmac); + } + } +} + +static void phytium_sdhc_error_occurred_handler(FSdif *const instance_p, void *args, u32 status, u32 dmac_status) +{ + struct usdhc_data *data = (struct usdhc_data *)args; + LOG_ERR("Error occur !!!"); + LOG_ERR("Status: 0x%x, dmac status: 0x%x.", status, dmac_status); + + if (status & FSDIF_INT_RE_BIT) + LOG_ERR("Response err. 0x%x", (uint32_t)FSDIF_INT_RE_BIT); + + if (status & FSDIF_INT_RTO_BIT) + LOG_ERR("Response timeout. 0x%x", (uint32_t)FSDIF_INT_RTO_BIT); + + if (dmac_status & FSDIF_DMAC_STATUS_DU) + LOG_ERR("Descriptor un-readable. 0x%x", (uint32_t)FSDIF_DMAC_STATUS_DU); + + if (status & FSDIF_INT_DCRC_BIT) + LOG_ERR("Data CRC error. 0x%x", (uint32_t)FSDIF_INT_DCRC_BIT); + + if (status & FSDIF_INT_RCRC_BIT) + LOG_ERR("Data CRC error. 0x%x", (uint32_t)FSDIF_INT_RCRC_BIT); + + /* Replace data_done by event */ + k_event_post(&data->irq_event,FSDIF_IRQ_BIT_CMD_DONE|FSDIF_IRQ_BIT_ERROR_OCCUR) ; +} + +/* + * Reset USDHC controller + */ +static int phytium_sdhc_reset(const struct device *dev) +{ + struct usdhc_data *data = dev->data; + FSdif *instance = &data->instance ; + + return (FSdifRestart(instance) == FSDIF_SUCCESS) ? 0 : -ETIMEDOUT; + +} + + +static int phytium_sdhc_set_io(const struct device *dev, struct sdhc_io *ios) +{ + struct usdhc_data *data = dev->data; + FSdif *instance = &data->instance; + uintptr base_addr = instance->config.base_addr; + bool is_drr = false; + + if ((ios->timing == SDHC_TIMING_DDR50) || (ios->timing == SDHC_TIMING_DDR52) || + (ios->timing == SDHC_TIMING_HS400)) + { + is_drr = true; + } + + LOG_DBG("SDHC I/O: bus width %d, clock %dHz, card power %s, voltage %s ddr %s\r\n", + ios->bus_width, ios->clock, ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF", + ios->signal_voltage == SD_VOL_1_8_V ? "1.8V" : "3.3V", is_drr ? "on" : "off"); + + if (data->cur_ios.clock != ios->clock) + { + if (FSDIF_SUCCESS != FSdifSetClkFreqByCalc(instance, is_drr, ios->clock)) + { + LOG_ERR("FSdifSetClkFreqByCalc failed\r\n"); + return -ENXIO; + } + } + + if (data->cur_ios.bus_width != ios->bus_width) + { + switch (ios->bus_width) + { + case SDHC_BUS_WIDTH1BIT: + FSdifSetCardBusWidth(instance, 1U); + break; + case SDHC_BUS_WIDTH4BIT: + FSdifSetCardBusWidth(instance, 4U); + break; + case SDHC_BUS_WIDTH8BIT: + FSdifSetCardBusWidth(instance, 8U); + break; + default: + return -ENOTSUP; + } + } + + if (data->cur_ios.signal_voltage != ios->signal_voltage) + { + switch (ios->signal_voltage) + { + case SD_VOL_3_3_V: + case SD_VOL_3_0_V: + FSdifSetVoltage1_8V(base_addr, FALSE); + break; + case SD_VOL_1_8_V: + FSdifSetVoltage1_8V(base_addr, TRUE); + break; + default: + return -ENOTSUP; + } + } + + memcpy(&(data->cur_ios), ios, sizeof(*ios)); + return 0; +} + + +static int phytium_sdhc_card_busy(const struct device *dev) +{ + struct usdhc_data *device_data = dev->data; + FSdif *instance = &device_data->instance ; + + return FSdifCheckCardBusy(instance) ? 1 : 0; +} + + +#define SPI_MASK ((1U << 4) | (2U << 4) | (3U << 4) | (4U << 4) | (5U << 4) | (6U << 4) | (7U << 4)) + +static void phytium_cmddata_convert_dri_data(struct sdhc_command *cmd, struct sdhc_data *data, FSdifCmdData *cmd_data) +{ + uint32_t raw_cmd = FSDIF_CMD_INDX_SET(cmd->opcode); + uint32_t response_type = cmd->response_type & ~SPI_MASK; + + if (cmd->opcode == SD_GO_IDLE_STATE) + { + raw_cmd |= FSDIF_CMD_INIT; + } + + if (cmd->opcode == SD_GO_INACTIVE_STATE) + { + raw_cmd |= FSDIF_CMD_STOP_ABORT; + } + + if (SD_RSP_TYPE_NONE != response_type) + { + raw_cmd |= FSDIF_CMD_RESP_EXP; + + if (response_type == SD_RSP_TYPE_R2) + { + raw_cmd |= FSDIF_CMD_RESP_LONG; + } + + if ((response_type != SD_RSP_TYPE_R3) && (response_type != SD_RSP_TYPE_R4)) + { + raw_cmd |= FSDIF_CMD_RESP_CRC; + } + } + + if (cmd->opcode == SD_VOL_SWITCH) + { + raw_cmd |= FSDIF_CMD_VOLT_SWITCH; + } + + if (data) + { + raw_cmd |= FSDIF_CMD_DAT_EXP; + + switch (cmd->opcode) + { + case SD_WRITE_SINGLE_BLOCK: + case SD_WRITE_MULTIPLE_BLOCK: + raw_cmd |= FSDIF_CMD_DAT_WRITE; + cmd_data->data_p->buf = data->data; + cmd_data->data_p->buf_dma = (uintptr_t)data->data; + break; + default: + cmd_data->data_p->buf = data->data; + /* This assumes that the data pointer can be used as a DMA address, which + * might not always be correct. */ + cmd_data->data_p->buf_dma = (uintptr_t)data->data; + break; + } + + cmd_data->data_p->blksz = data->block_size; + cmd_data->data_p->blkcnt = data->blocks; + cmd_data->data_p->datalen = data->block_size * data->blocks; + } + + cmd_data->rawcmd = raw_cmd; + cmd_data->cmdidx = cmd->opcode; + cmd_data->cmdarg = cmd->arg; +} + +static int phytium_sdhc_request(const struct device *dev, struct sdhc_command *cmd, struct sdhc_data *data) +{ + struct usdhc_data *device_data = dev->data; + struct usdhc_config *device_config = (struct usdhc_config *)dev->config; + FSdif *instance = &device_data->instance ; + FSdifCmdData *cmd_data = &device_data->cmd_data ; + uint32_t timeout = 5000U ; + uint32_t wait_timeout_cnt = 0 ; + uint32_t events = 0; + uint32_t end_event = 0; /* 0 is init ,1 is finish ,2 is err ocurr */ + uint32_t wait_mask = 0; + + if (card_polling_busy(dev, timeout)) + { + return -EBUSY; + } + + if (instance->config.non_removable) + { + /* ignore micro SD detect command, not in eMMC spec. */ + if ((SD_APP_SEND_OP_COND == cmd->opcode) || + (SD_APP_CMD == cmd->opcode)) + { + return 0; + } + + /* ignore mmcsd_send_if_cond(CMD-8) which will failed for eMMC + but check cmd arg to let SEND_EXT_CSD (CMD-8) run */ + if ((SD_SEND_IF_COND == cmd->opcode) && + (0x1aa == cmd->arg)) + { + return 0; + } + } + + /* add send cmd23 */ + if(cmd->opcode == SD_WRITE_MULTIPLE_BLOCK||cmd->opcode == SD_READ_MULTIPLE_BLOCK) + { + if(card_setblcok(dev,data->blocks)) + { + LOG_ERR("FSdifDMATransfer is error") ; + return -EHOSTUNREACH; + } + } + + /* init event data is zero */ + if(device_config->is_enable_irq) + { + k_event_set(&device_data->irq_event,0) ; + } + + memset(&device_data->cmd_data,0,sizeof(FSdifCmdData)) ; + if(data) + { + memset(&device_data->trans_data,0,sizeof(FSdifData)) ; + cmd_data->data_p = &device_data->trans_data ; + wait_mask = FSDIF_IRQ_BIT_CMD_DONE | FSDIF_IRQ_BIT_DATA_DONE ; + } + else + { + cmd_data->data_p = NULL ; + wait_mask = FSDIF_IRQ_BIT_CMD_DONE ; + } + + phytium_cmddata_convert_dri_data(cmd,data,cmd_data) ; + + if(instance->config.trans_mode == FSDIF_IDMA_TRANS_MODE) + { + if (cmd_data->data_p) + { + if (FSDIF_SUCCESS != FSdifSetupDMADescriptor(instance, cmd_data->data_p)) + { + LOG_ERR("FSdifSetupDMADescriptor is failed"); + return -EHOSTUNREACH; + } + } + + if (FSDIF_SUCCESS != FSdifDMATransfer(instance, cmd_data)) + { + LOG_ERR("FSdifDMATransfer is error") ; + return -EHOSTUNREACH; + } + } + else + { + if (FSDIF_SUCCESS != FSdifPIOTransfer(instance, cmd_data)) + { + LOG_ERR("FSdifPIOTransfer is error") ; + return -EHOSTUNREACH; + } + } + + if(device_config->is_enable_irq) + { + do + { + events = k_event_wait_all(&device_data->irq_event,wait_mask,false,K_MSEC(1)) ; + if(events & FSDIF_IRQ_BIT_ERROR_OCCUR) + { + end_event = 2 ; + break ; + } + else if((events & wait_mask) == wait_mask) + { + end_event = 1 ; + break ; + } + else + { + wait_timeout_cnt ++ ; + end_event = 3 ; + } + }while (wait_timeout_cnt < 0xffffff) ; + + if(end_event == 2) + { + return -EIO ; + } + else if(end_event == 3) + { + return -ETIME ; + } + + } + else + { + if (FSDIF_SUCCESS != FSdifPollWaitTransferEnd(instance, cmd_data)) + { + LOG_ERR("FSdifPollWaitTransferEnd failed \r\n"); + return -ETIMEDOUT; + } + } + /* wait event is over */ + if(FSDIF_SUCCESS != FSdifGetCmdResponse(instance, cmd_data)) + { + LOG_ERR("FSdifGetCmdResponse is error") ; + + if(cmd_data->data_p) + { + card_stoptrans(dev) ; + + while (timeout > 0) { + if (!phytium_sdhc_card_busy(dev)) { + break; + } + /* Wait 125us before polling again */ + k_busy_wait(125); + timeout -= 125; + } + if (timeout <= 0) { + LOG_DBG("Card did not idle after CMD12"); + k_mutex_unlock(&device_data->access_mutex); + return -ETIMEDOUT; + } + + return -ETIMEDOUT; + } + + return -ETIMEDOUT; + } + + if(SD_RSP_TYPE_NONE != cmd->response_type) + { + memcpy(cmd->response,&cmd_data->response,sizeof(u32) * 4) ; + } + + return 0; +} + + + +/* Stops transmission after failed command with CMD12 */ +static void card_stoptrans(const struct device *dev) +{ + struct sdhc_command cmd = {0}; + + cmd.opcode = SD_STOP_TRANSMISSION; + cmd.arg = 0; + + cmd.response_type = (SD_RSP_TYPE_R1b); + + phytium_sdhc_request(dev, &cmd, NULL) ; + +} + +static int card_setblcok(const struct device *dev, uint32_t num_blocks) +{ + struct sdhc_command cmd = {0}; + + /* + * See the note in card_read() above. We will not issue CMD23 + * or CMD12, and expect the host to handle those details. + */ + cmd.opcode = SD_SET_BLOCK_COUNT; + + cmd.arg = num_blocks; + + cmd.response_type = (SD_RSP_TYPE_R1); + + return phytium_sdhc_request(dev, &cmd, NULL) ; +} + +static int phytium_sdhc_get_card_present(const struct device *dev) +{ + struct usdhc_data *data = dev->data; + FSdif *instance = &data->instance ; + + data->card_present = FSdifCheckCardExists(instance) ? 1 : 0; + return data->card_present; +} + + +static int phytium_sdhc_get_host_props(const struct device *dev, + struct sdhc_host_props *props) +{ + struct usdhc_data *data = dev->data; + + memcpy(props, &data->props, sizeof(struct sdhc_host_props)); + return 0; +} + +static int phytium_sdhc_isr(const struct device *dev) +{ + // const struct usdhc_config *cfg = dev->config; + struct usdhc_data *data = dev->data; + FSdif *instance = &data->instance ; + + FSdifInterruptHandler(0, instance); + return 0; +} + + +static void phytium_sdhc_init_host_props(const struct device *dev) +{ + struct usdhc_config *cfg = (struct usdhc_config *)dev->config; + struct usdhc_data *data = (struct usdhc_data *)dev->data; + struct sdhc_host_props *props = &data->props; + + memset(props, 0, sizeof(struct sdhc_host_props)); + props->f_max = cfg->max_bus_freq; + props->f_min = cfg->min_bus_freq; + + props->host_caps.vol_180_support = false; + props->host_caps.vol_300_support = true; + props->host_caps.vol_330_support = true; + props->host_caps.suspend_res_support = false; + props->host_caps.high_spd_support = true; + + props->host_caps.ddr50_support = false; + props->host_caps.sdr104_support = false; + props->host_caps.sdr50_support = false; + + props->host_caps.bus_4_bit_support = true; + props->host_caps.bus_8_bit_support = false; + props->host_caps.hs200_support = false; + props->host_caps.hs400_support = false; +} + + +void phytium_relax_delay(void) +{ + k_usleep(1); +} + + +static int card_polling_busy(const struct device *dev, int timeout_us) +{ + struct usdhc_data *device_data = dev->data; + FSdif *instance = &device_data->instance; + int wait_counter = 0; + + while (FSdifCheckCardBusy(instance)) + { + if (wait_counter > timeout_us) + { + LOG_ERR("Failed to wait card not busy\r\n"); + return EBUSY; + } + + /* busy waiting here will actually faster */ + phytium_relax_delay(); /* wait 1us here */ + wait_counter++; + } + + return 0; +} + +static void phytium_sdhc_pad_delay_init(FIOPadCtrl * iopad_ctrl) +{ +#if defined(CONFIG_SOC_PD2308) + #define FSDIF_0_SD_CCLK_OUT_DELAY FIOPAD_BV65_REG1_OFFSET + + /* fix this for firmwire */ + FtOut32(iopad_ctrl->config.base_address + FSDIF_0_SD_CCLK_OUT_DELAY, 0x5f00); +#endif +} + +static int phytium_usdhc_init(const struct device *dev) +{ + struct usdhc_config *cfg = (struct usdhc_config *)dev->config; + struct usdhc_data *data = (struct usdhc_data *)dev->data; + FSdifConfig sdhc_cfg; + FIOPadConfig io_config = {0} ; + + /* init base */ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + /* control init */ + sdhc_cfg.base_addr = DEVICE_MMIO_GET(dev) ; + sdhc_cfg.instance_id = cfg->instance_id; /* Device instance id */ + LOG_DBG("sdhc_cfg.instance_id is %d \r\n",sdhc_cfg.instance_id) ; + + sdhc_cfg.non_removable = cfg->non_removeable ; /* No removeable media, e.g eMMC */ +#if CONFIG_PHYTIUM_USDHC_DMA_SUPPORT + sdhc_cfg.trans_mode = FSDIF_IDMA_TRANS_MODE; /* Trans mode, DMA */ +#else + sdhc_cfg.trans_mode = FSDIF_PIO_TRANS_MODE; /* Trans mode, PIO */ +#endif + sdhc_cfg.src_clk_rate = FSDIF_CLK_FREQ_HZ; + + /* init pio init */ + io_config.instance_id = cfg->pio_id ; + + device_map(&io_config.base_address, + cfg->pio_base, + cfg->pio_length, + K_MEM_CACHE_NONE); + + if(0 != FIOPadCfgInitialize(&data->iopad_ctrl, &io_config)) + { + LOG_ERR("FIOPadCfgInitialize is error") ; + } + + phytium_sdhc_pad_delay_init(&data->iopad_ctrl); + + if(0 != FSdifCfgInitialize(&data->instance,&sdhc_cfg)) + { + LOG_ERR("FSdifCfgInitialize is error") ; + } + data->instance.relax_handler = phytium_relax_delay ; + + phytium_sdhc_init_host_props(dev) ; + /* irq init */ + if(cfg->is_enable_irq) + { + if(cfg->irq_config_func) + { + FSdifRegisterEvtHandler(&data->instance, FSDIF_EVT_CARD_DETECTED, phytium_sdhc_card_detect_handler, (void *)data); + FSdifRegisterEvtHandler(&data->instance, FSDIF_EVT_ERR_OCCURE, phytium_sdhc_error_occurred_handler, (void *)data); + FSdifRegisterEvtHandler(&data->instance, FSDIF_EVT_CMD_DONE, phytium_sdhc_command_done_handler, (void *)data); + FSdifRegisterEvtHandler(&data->instance, FSDIF_EVT_DATA_DONE, phytium_sdhc_data_done_handler, (void *)data); + cfg->irq_config_func(dev) ; + } + } + +#if CONFIG_PHYTIUM_USDHC_DMA_SUPPORT + + if (sdhc_cfg.trans_mode == FSDIF_IDMA_TRANS_MODE) + { + + if(FSdifSetIDMAList(&data->instance,data->usdhc_dma_descriptor,(uintptr)data->usdhc_dma_descriptor,CONFIG_PHYTIUM_SDIF_DMA_DESC_LENGTH)) + { + LOG_ERR("Init dma is error ") ; + return -EPERM; + } + } + +#endif + + /* init host_io */ + memset(&data->host_io, 0, sizeof(data->host_io)); + /* access_mutex */ + k_mutex_init(&data->access_mutex); + /* transfer_sem */ + k_event_init(&data->irq_event) ; + return 0 ; +} + +static const struct sdhc_driver_api usdhc_api = { + .reset = phytium_sdhc_reset, + .request = phytium_sdhc_request, + .set_io = phytium_sdhc_set_io, + .get_card_present = phytium_sdhc_get_card_present, + .execute_tuning = NULL, + .card_busy = phytium_sdhc_card_busy, + .get_host_props = phytium_sdhc_get_host_props, +}; + +#ifdef CONFIG_NOCACHE_MEMORY +#define PHYTIUM_USDHC_NOCACHE_TAG __attribute__((__section__(".nocache"))); +#else +#define PHYTIUM_USDHC_NOCACHE_TAG +#endif + +#if CONFIG_PHYTIUM_USDHC_DMA_SUPPORT +#define PHYTIUM_USDHC_DMA_BUFFER_DEFINE(n) \ + static FSdifIDmaDesc __aligned(FSDIF_DMA_DESC_ALIGMENT) \ + usdhc_##n##_dma_descriptor[CONFIG_PHYTIUM_SDIF_DMA_DESC_LENGTH]\ + PHYTIUM_USDHC_NOCACHE_TAG; +#define PHYTIUM_USDHC_DMA_BUFFER_INIT(n) \ + .usdhc_dma_descriptor = usdhc_##n##_dma_descriptor, \ + .dma_descriptor_len = CONFIG_PHYTIUM_SDIF_DMA_DESC_LENGTH, + +#else +#define PHYTIUM_USDHC_DMA_BUFFER_DEFINE(n) +#define PHYTIUM_USDHC_DMA_BUFFER_INIT(n) +#endif /* CONFIG_PHYTIUM_USDHC_DMA_SUPPORT */ + +#define PHYTIUM_SDHC_INIT(n) \ + static void usdhc_##n##_irq_config_func(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + phytium_sdhc_isr, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + static const struct usdhc_config usdhc_##n##_config = { \ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ + .instance_id = n, \ + .no_180_vol = DT_INST_PROP(n, no_1_8_v), \ + .mmc_hs200_1_8v = DT_INST_PROP(n, mmc_hs200_1_8v), \ + .mmc_hs400_1_8v = DT_INST_PROP(n, mmc_hs400_1_8v), \ + .pio_id = DT_INST_PROP(n, pio_id), \ + .pio_base = DT_INST_PROP(n, pio_base), \ + .pio_length = DT_INST_PROP(n, pio_length), \ + .is_enable_irq = DT_INST_PROP(n, is_enable_irq),\ + .non_removeable = DT_INST_PROP(n, non_removeable),\ + .max_bus_freq = DT_INST_PROP(n, max_bus_freq),\ + .min_bus_freq = DT_INST_PROP(n, min_bus_freq),\ + .irq_config_func = usdhc_##n##_irq_config_func ,\ + }; \ + \ + \ + PHYTIUM_USDHC_DMA_BUFFER_DEFINE(n) \ + \ + static struct usdhc_data usdhc_##n##_data = { \ + .card_present = false, \ + PHYTIUM_USDHC_DMA_BUFFER_INIT(n) \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, \ + &phytium_usdhc_init, \ + NULL, \ + &usdhc_##n##_data, \ + &usdhc_##n##_config, \ + POST_KERNEL, \ + CONFIG_SDHC_INIT_PRIORITY, \ + &usdhc_api); + +DT_INST_FOREACH_STATUS_OKAY(PHYTIUM_SDHC_INIT) + + + diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 9ac2f22920d5ef64697a6d6009144b0ba190cf79..e59851875bbb1a06270b844b9411ac2e71138f7b 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_STM32 uart_stm32.c) zephyr_library_sources_ifdef(CONFIG_UART_SAM0 uart_sam0.c) zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c) zephyr_library_sources_ifdef(CONFIG_UART_PL011 uart_pl011.c) +# zephyr_library_sources_ifdef(CONFIG_PHYTIUM_UART_PL011 uart_phytium_pl011.c) zephyr_library_sources_ifdef(CONFIG_UART_QUICKLOGIC_USBSERIALPORT_S3B uart_ql_usbserialport_s3b.c) zephyr_library_sources_ifdef(CONFIG_UART_RV32M1_LPUART uart_rv32m1_lpuart.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index faa150237c59332e494d22890e04eacfc5211969..2d6c9b45d556260895dc3d3a0d0bc4c1ab16e712 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -278,6 +278,8 @@ rsource "Kconfig.ene" rsource "Kconfig.rzt2m" +rsource "kconfig.phytium_pl011" + source "drivers/serial/Kconfig.renesas_ra8" endif # SERIAL diff --git a/drivers/serial/kconfig.phytium_pl011 b/drivers/serial/kconfig.phytium_pl011 new file mode 100644 index 0000000000000000000000000000000000000000..6e9a7912524394f61188a3f9021966464eae2aa3 --- /dev/null +++ b/drivers/serial/kconfig.phytium_pl011 @@ -0,0 +1,21 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +menuconfig PHYTIUM_UART_PL011 + bool "PHYTIUM PL011 UART Driver" + default y + select SERIAL_HAS_DRIVER + help + This option enables the UART driver for the PL011 diff --git a/drivers/serial/uart_phytium_pl011.c b/drivers/serial/uart_phytium_pl011.c new file mode 100644 index 0000000000000000000000000000000000000000..e6f04b16b47563309ea534a2d2356ad8039e05a4 --- /dev/null +++ b/drivers/serial/uart_phytium_pl011.c @@ -0,0 +1,148 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#define DT_DRV_COMPAT phytium_pl011 /* phytium,pl011 */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct phytium_pl011_data { + DEVICE_MMIO_RAM; + uint32_t baud_rate; +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + uart_irq_callback_user_data_t irq_cb; + void *irq_cb_data; +#endif + FPl011 instance ; +}; + +struct phytium_pl011_config { + DEVICE_MMIO_ROM; + uint32_t instance_id; + uint32_t sys_clk_freq; +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + /*Interrupt initialization function through the device tree*/ + uart_irq_config_func_t irq_config_func; +#endif +}; + +static int pl011_poll_in(const struct device *dev, unsigned char *c) +{ + struct phytium_pl011_data *data = dev->data; + FPl011 *uart_p = &data->instance ; + + if(FUART_RECEIVEDATAEMPTY(uart_p->config.base_address)) + { + return -1 ; + } + + *c = FPl011RecvByte(uart_p->config.base_address) ; + + return (FUART_RECEIVEDATAEMPTY(uart_p->config.base_address) == 0); +} + +static void pl011_poll_out(const struct device *dev, + unsigned char c) +{ + struct phytium_pl011_data *data = dev->data; + FPl011 *uart_p = &data->instance ; + + FPl011SendByte(uart_p->config.base_address,c) ; +} + +static const struct uart_driver_api pl011_driver_api = { + .poll_in = pl011_poll_in, + .poll_out = pl011_poll_out, +}; + +static int pl011_init(const struct device *dev) +{ + const struct phytium_pl011_config *config = dev->config; + struct phytium_pl011_data *data = dev->data; + FPl011Config pl011_config = {0} ; + FError driver_ret ; + + FPl011Format format = + { + .baudrate = FPL011_BAUDRATE, + .data_bits = FPL011_FORMAT_WORDLENGTH_8BIT, + .parity = FPL011_FORMAT_NO_PARITY, + .stopbits = FPL011_FORMAT_1_STOP_BIT + }; + + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); + + /* Id of device*/ + pl011_config.instance_id = config->instance_id; + pl011_config.base_address = DEVICE_MMIO_GET(dev) ; + pl011_config.ref_clock_hz = config->sys_clk_freq; + pl011_config.baudrate = data->baud_rate; + + driver_ret = FPl011CfgInitialize(&data->instance,&pl011_config) ; + + if(driver_ret) + { + return -1 ; + } + + driver_ret = FPl011SetDataFormat(&data->instance, &format); + + if(driver_ret) + { + return -2 ; + } + + /* set UART */ + FPl011SetOptions(&data->instance, FPL011_OPTION_UARTEN | FPL011_OPTION_FIFOEN | FPL011_OPTION_RXEN | FPL011_OPTION_TXEN | FPL011_OPTION_DTR | FPL011_OPTION_RTS); + + return 0; +} + + + + +#define PL011_CONFIG_PORT(n) \ + static struct phytium_pl011_config pl011_cfg_port_##n = { \ + DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ + .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ + .instance_id = n \ + }; + + +#define PHYTIUM_PL011_INIT(n) \ + PL011_CONFIG_PORT(n) \ + \ + static struct phytium_pl011_data pl011_data_port_##n = { \ + .baud_rate = DT_INST_PROP(n, current_speed), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &pl011_init, \ + NULL, \ + &pl011_data_port_##n, \ + &pl011_cfg_port_##n, \ + PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, \ + &pl011_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(PHYTIUM_PL011_INIT) \ No newline at end of file diff --git a/dts/arm/phytium/pe2202_aarch32.dtsi b/dts/arm/phytium/pe2202_aarch32.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6a6b25f2e97f3c457df1ddd9fd70ab0644a76252 --- /dev/null +++ b/dts/arm/phytium/pe2202_aarch32.dtsi @@ -0,0 +1,168 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x200>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x201>; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + // ppi =+ 16, 13 == 29 安全物理定时器中断, 14 == 30 非安全物理定时器中断 + interrupts = , + , + , + ; + }; + + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gic>; + + gic: interrupt-controller@30800000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x00 0x30800000 0x00 0x40000>, + <0x00 0x30880000 0x00 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + #size-cells = <0x02>; + #address-cells = <0x02>; + }; + + pinctrl: pinctrl@32B30000 { + compatible = "phytium,pinctrl"; + reg = <0x00 0x32B30000 0x00 0x2000>; + status = "okay"; + }; + + uart1: uart@2800d000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800d000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + clocks = <&uartclk>; + }; + + uart2: uart@2800E000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800E000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_1"; + clocks = <&uartclk>; + }; + + sdhc0: sdhc@28000000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28000000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <25000000>; + min-bus-freq = <400000>; + }; + + + sdhc1: sdhc@28001000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28001000 0x00 0x1000>; + pio-base = <0x32B30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + }; + + + xmac0: xmac@3200C000 { + compatible = "phytium,xmac"; + reg = <0x00 0x3200C000 0x00 0x2000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + phy-poll-interval = <1000>; + clock-frequency = <50000000>; + phy-speed = <1000>; + interface-mode = <0>; + dma-brust-length = <16>; + max-queue-num = <1>; + rx-buffer-descriptors = <128>; + tx-buffer-descriptors = <32>; + rx-buffer-size = <1600>; + tx-buffer-size = <1600>; + phy-autonegotiation; + enable-fdx; + disable-reject-fcs-crc-errors; + }; + + pcie0: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x00 0x40000000 0x00 0x10000000>; + #size-cells = <0x02>; + #address-cells = <0x03>; + ranges = <0x1000000 0x00 0x50000000 0x00 0x50000000 0x00 0x08000000 + 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x27ffffff + 0x3000000 0x10 0x00 0x10 0x00 0x1f 0xffffffff>; + bus-range = <0x00 0xff>; + }; + + /* 256MB DDR */ + sram0: memory@80100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x00 0x80100000 0x00 0x10000000>; + }; + }; +}; diff --git a/dts/arm/phytium/pe2204_aarch32.dtsi b/dts/arm/phytium/pe2204_aarch32.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..67f4bcc44aec1b6d1c905eed430646c856e6d358 --- /dev/null +++ b/dts/arm/phytium/pe2204_aarch32.dtsi @@ -0,0 +1,178 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x200>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x201>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "phytium,ftc664"; + reg = <0 0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "phytium,ftc664"; + reg = <0 0x100>; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + // ppi =+ 16, 13 == 29 Security physical timer interrupt, 14 == 30 Non secure physical timer interrupt + interrupts = , + , + , + ; + }; + + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gic>; + + gic: interrupt-controller@30800000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x00 0x30800000 0x00 0x40000>, + <0x00 0x30880000 0x00 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + #size-cells = <0x02>; + #address-cells = <0x02>; + }; + + pinctrl: pinctrl@32b30000 { + compatible = "phytium,pinctrl"; + reg = <0x00 0x32b30000 0x00 0x2000>; + status = "okay"; + }; + + uart1: uart@2800d000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800d000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + clocks = <&uartclk>; + }; + + uart2: uart@2800e000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800e000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_1"; + clocks = <&uartclk>; + }; + + sdhc0: sdhc@28000000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28000000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <25000000>; + min-bus-freq = <400000>; + }; + + xmac0: xmac@3200C000 { + compatible = "phytium,xmac"; + reg = <0x00 0x3200C000 0x00 0x2000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + phy-poll-interval = <5000>; + clock-frequency = <50000000>; + phy-speed = <1000>; + interface-mode = <0>; + dma-brust-length = <16>; + max-queue-num = <1>; + rx-buffer-descriptors = <128>; + tx-buffer-descriptors = <128>; + rx-buffer-size = <1600>; + tx-buffer-size = <1600>; + phy-autonegotiation; + enable-fdx; + disable-reject-fcs-crc-errors; + }; + + sdhc1: sdhc@28001000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28001000 0x00 0x1000>; + pio-base = <0x32B30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + }; + + /* 512MB DDR */ + sram0: memory@80100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x00 0x80100000 0x00 0x20000000>; + }; + + pcie0: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x00 0x40000000 0x00 0x10000000>; + #size-cells = <0x02>; + #address-cells = <0x03>; + ranges = <0x1000000 0x00 0x50000000 0x00 0x50000000 0x00 0x08000000 + 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x27ffffff + 0x3000000 0x10 0x00 0x10 0x00 0x1f 0xffffffff>; + bus-range = <0x00 0xff>; + }; + }; +}; diff --git a/dts/arm64/phytium/pe2202.dtsi b/dts/arm64/phytium/pe2202.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f7b0ea0603f1be255158de7d6b005400a4d40c05 --- /dev/null +++ b/dts/arm64/phytium/pe2202.dtsi @@ -0,0 +1,170 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x200>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x201>; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + // ppi =+ 16, 13 == 29 安全物理定时器中断, 14 == 30 非安全物理定时器中断 + interrupts = , + , + , + ; + }; + + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gic>; + + gic: interrupt-controller@30800000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x00 0x30800000 0x00 0x40000>, + <0x00 0x30880000 0x00 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + #size-cells = <0x02>; + #address-cells = <0x02>; + }; + + pinctrl: pinctrl@32b30000 { + compatible = "phytium,pinctrl"; + reg = <0x00 0x32b30000 0x00 0x2000>; + status = "okay"; + }; + + uart1: uart@2800d000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800d000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + clocks = <&uartclk>; + }; + + uart2: uart@2800e000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800e000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_1"; + clocks = <&uartclk>; + }; + + sdhc0: sdhc@28000000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28000000 0x00 0x1000>; + pio-base = <0x32b30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <52000000>; + min-bus-freq = <400000>; + non-removeable; + }; + + + sdhc1: sdhc@28001000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28001000 0x00 0x1000>; + pio-base = <0x32b30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + }; + + + xmac0: xmac@3200c000 { + compatible = "phytium,xmac"; + reg = <0x00 0x3200c000 0x00 0x2000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + phy-poll-interval = <1000>; + clock-frequency = <50000000>; + phy-speed = <1000>; + interface-mode = <0>; + dma-brust-length = <16>; + max-queue-num = <1>; + rx-buffer-descriptors = <128>; + tx-buffer-descriptors = <32>; + rx-buffer-size = <1600>; + tx-buffer-size = <1600>; + phy-autonegotiation; + enable-fdx; + disable-reject-fcs-crc-errors; + }; + + pcie0: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x00 0x40000000 0x00 0x10000000>; + #size-cells = <0x02>; + #address-cells = <0x03>; + ranges = <0x1000000 0x00 0x50000000 0x00 0x50000000 0x00 0x08000000 + 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x27ffffff + 0x3000000 0x10 0x00 0x10 0x00 0x1f 0xffffffff>; + bus-range = <0x00 0xff>; + }; + + /* 256MB DDR */ + sram0: memory@80100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x00 0x80100000 0x00 0x10000000>; + }; + }; +}; diff --git a/dts/arm64/phytium/pe2204.dtsi b/dts/arm64/phytium/pe2204.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..45b1dda2f99e28a77b625b9413c23f17709ab36c --- /dev/null +++ b/dts/arm64/phytium/pe2204.dtsi @@ -0,0 +1,180 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x200>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,ftc310"; + reg = <0 0x201>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "phytium,ftc664"; + reg = <0 0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "phytium,ftc664"; + reg = <0 0x100>; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + // ppi =+ 16, 13 == 29 Security physical timer interrupt, 14 == 30 Non secure physical timer interrupt + interrupts = , + , + , + ; + }; + + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gic>; + + gic: interrupt-controller@30800000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x00 0x30800000 0x00 0x40000>, + <0x00 0x30880000 0x00 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + #size-cells = <0x02>; + #address-cells = <0x02>; + }; + + pinctrl: pinctrl@32b30000 { + compatible = "phytium,pinctrl"; + reg = <0x00 0x32b30000 0x00 0x2000>; + status = "okay"; + }; + + uart1: uart@2800d000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800d000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + clocks = <&uartclk>; + }; + + uart2: uart@2800e000 { + compatible = "arm,pl011"; + reg = <0x00 0x2800e000 0x00 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_1"; + clocks = <&uartclk>; + }; + + sdhc0: sdhc@28000000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28000000 0x00 0x1000>; + pio-base = <0x32b30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <52000000>; + min-bus-freq = <400000>; + non-removeable; + }; + + sdhc1: sdhc@28001000 { + compatible = "phytium,sdhc"; + reg = <0x00 0x28001000 0x00 0x1000>; + pio-base = <0x32b30000>; + status = "disabled"; + interrupts = ; + max-current-330 = <1020>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + }; + + xmac0: xmac@3200c000 { + compatible = "phytium,xmac"; + reg = <0x00 0x3200c000 0x00 0x2000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + phy-poll-interval = <5000>; + clock-frequency = <50000000>; + phy-speed = <1000>; + interface-mode = <0>; + dma-brust-length = <16>; + max-queue-num = <1>; + rx-buffer-descriptors = <128>; + tx-buffer-descriptors = <128>; + rx-buffer-size = <1600>; + tx-buffer-size = <1600>; + phy-autonegotiation; + enable-fdx; + disable-reject-fcs-crc-errors; + }; + + /* 512MB DDR */ + sram0: memory@80100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x00 0x80100000 0x00 0x20000000>; + }; + + pcie0: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x00 0x40000000 0x00 0x10000000>; + #size-cells = <0x02>; + #address-cells = <0x03>; + ranges = <0x1000000 0x00 0x50000000 0x00 0x50000000 0x00 0x08000000 + 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x27ffffff + 0x3000000 0x10 0x00 0x10 0x00 0x1f 0xffffffff>; + bus-range = <0x00 0xff>; + }; + }; +}; diff --git a/dts/bindings/cpu/phytium,ftc310.yaml b/dts/bindings/cpu/phytium,ftc310.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e1f9c01fcc313fa75f9ebecb668cdb6c1e1de3f8 --- /dev/null +++ b/dts/bindings/cpu/phytium,ftc310.yaml @@ -0,0 +1,20 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium ftc310 arm CPU + +compatible: "phytium,ftc310" + +include: cpu.yaml \ No newline at end of file diff --git a/dts/bindings/cpu/phytium,ftc663.yaml b/dts/bindings/cpu/phytium,ftc663.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5e8e7ef56f1be9a7434b16862a32f5908c49aae0 --- /dev/null +++ b/dts/bindings/cpu/phytium,ftc663.yaml @@ -0,0 +1,20 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium ftc663 arm CPU + +compatible: "phytium,ftc663" + +include: cpu.yaml \ No newline at end of file diff --git a/dts/bindings/cpu/phytium,ftc862.yaml b/dts/bindings/cpu/phytium,ftc862.yaml new file mode 100644 index 0000000000000000000000000000000000000000..60dae60453edcb437afae9f67d726d10d57542cb --- /dev/null +++ b/dts/bindings/cpu/phytium,ftc862.yaml @@ -0,0 +1,20 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium ftc862 arm CPU + +compatible: "phytium,ftc862" + +include: cpu.yaml \ No newline at end of file diff --git a/dts/bindings/ethernet/phytium,gmac.yaml b/dts/bindings/ethernet/phytium,gmac.yaml new file mode 100644 index 0000000000000000000000000000000000000000..eb23c5d65c39bc8a5ca1a90423425cfd90e6b2fd --- /dev/null +++ b/dts/bindings/ethernet/phytium,gmac.yaml @@ -0,0 +1,88 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium gmac Ethernet controller + +compatible: "phytium,gmac" + +include: ethernet-controller.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + phy-speed: + type: int + required: true + description: | + Nominal link speed. If no PHY is managed by an instance of this driver, + the respective controller will be configured to match the link speed + specified here. If a PHY is managed by the driver, advertisement of + the link speed specified here will be requested. If the optional pro- + perty advertise-lower-link-speeds is set, advertisement of the link + speed specified here plus any valid link speed below this value will + be requested. + enum: + - 10 + - 100 + - 1000 + - 10000 + + autonegotiation: + type: int + required: true + enum: + - 0 + - 1 + + phy_duplex: + type: int + required: true + enum: + - 0 + - 1 + + + phy-poll-interval: + type: int + required: true + description: | + PHY status polling interval in milliseconds for a driver instance + managing an associated PHY. + + handle-rx-in-isr: + type: boolean + description: | + Moves the handling of the frame received interrupt including the + transfer of packet data from the DMA to network packet buffers and + the subsequent propagation of the received packets to the network + stack into the context of the ISR. Due to the unpredictability of + the runtime of the ISR whenever large amounts of data are received, + handling of the RX interrupt is normally deferred to the context + of the system work queue. + + + handle-tx-in-workq: + type: boolean + description: | + Moves the handling of the frame transmission done interrupt into the + context of the system work queue. By default, TX done handling is per- + formed in the context of the ISR, as it only involves a limited number + of memory accesses. This option CAN NOT be used if any component ex- + ists within the current system setup that triggers the transmission + of packets from within the context of the system work queue! diff --git a/dts/bindings/ethernet/phytium,xmac.yaml b/dts/bindings/ethernet/phytium,xmac.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a17038ebbe8f60e4c00f91a034e0a7732809d06b --- /dev/null +++ b/dts/bindings/ethernet/phytium,xmac.yaml @@ -0,0 +1,233 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium xmac Ethernet controller + +compatible: "phytium,xmac" + +include: ethernet-controller.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + clock-frequency: + type: int + required: true + description: | + Specifies the base clock frequency from which the XMAC's TX clock + frequency . + + phy-poll-interval: + type: int + required: true + description: | + PHY status polling interval in milliseconds for a driver instance + managing an associated PHY. + + phy-speed: + type: int + required: true + description: | + Nominal link speed. If no PHY is managed by an instance of this driver, + the respective controller will be configured to match the link speed + specified here. If a PHY is managed by the driver, advertisement of + the link speed specified here will be requested. If the optional pro- + perty advertise-lower-link-speeds is set, advertisement of the link + speed specified here plus any valid link speed below this value will + be requested. + enum: + - 10 + - 100 + - 1000 + - 10000 + + + interface-mode: + type: int + required: true + description: | + Specifies the interface mode for the Xmac. Each mode corresponds to a different type of media-independent interface that determines how the Ethernet PHY is connected to the MAC. The available modes are: + - 0: SGMII (Serial Gigabit Media Independent Interface), a serial version of the Gigabit Media Independent Interface that is used for Gigabit Ethernet connections. + - 1: RMII (Reduced Media Independent Interface), a reduced version of the Media Independent Interface designed for 10/100Mbps Ethernet connections with a reduced number of signal lines. + - 2: RGMII (Reduced Gigabit Media Independent Interface), a version of the Gigabit Media Independent Interface designed for 10/100/1000Mbps Ethernet connections with a reduced number of signal lines. + - 3: USXGMII (Universal Serial 10 Gigabit Media Independent Interface), a serial interface designed for speeds beyond 1Gbps, supporting a range of speeds up to 10Gbps over a single pair of copper or optical fiber. + enum: + - 0 + - 1 + - 2 + - 3 + + + + dma-brust-length: + type: int + required: true + description: | + Defines the burst length for DMA (Direct Memory Access) operations in the Xmac driver. + The burst length specifies the maximum number of words the DMA controller can transfer in a single burst. + Adjusting this parameter can impact the efficiency of data transfers between the Ethernet MAC and the system memory, + potentially affecting overall throughput and latency. A value of 16 indicates that the DMA controller is configured to transfer up to 16 words in a single burst. + Choosing the optimal burst length depends on the specific characteristics of the system, including the DMA controller's capabilities and the memory system's response to burst accesses. + enum: + - 16 + + + max-queue-num: + type: int + required: true + description: | + Specifies the maximum number of queue slots available for managing Ethernet frames in the Xmac driver. + This parameter determines the capacity of the driver to handle multiple Ethernet frames concurrently, + which can influence the efficiency of packet processing, especially under high network traffic conditions. + A value of 1 indicates that the driver is configured to manage Ethernet frames using a single queue. + This configuration is suitable for simpler network setups or systems with lower traffic demands. + Implementing multiple queues can be advantageous in systems that require high throughput and efficient traffic management, + but this comes at the cost of increased complexity in queue management. + enum: + - 1 + + + phy-autonegotiation: + type: boolean + description: | + Determines whether the PHY (Physical Layer Transceiver) should use autonegotiation to automatically select the speed and duplex mode of the Ethernet connection. + When enabled (`true`), the PHY will communicate with the link partner (typically a switch, router, or another network device) to determine the best mutual settings for speed (10/100/1000 Mbps) and duplex mode (half or full duplex). + This process ensures compatibility and optimizes the connection for the best possible performance. + When disabled (`false`), the PHY will not initiate or respond to autonegotiation attempts, and the speed and duplex mode must be manually configured to match the link partner's settings, potentially reducing flexibility and compatibility. + + + enable-fdx: + type: boolean + description: | + Indicates whether the PHY (Physical Layer Transceiver) should operate in full-duplex mode. + In full-duplex mode (`true`), the Ethernet connection supports simultaneous bi-directional data transmission, allowing data to be sent and received at the same time, + effectively doubling the potential throughput compared to half-duplex. + This mode is ideal for high-speed networks where data collisions are managed and can significantly enhance network performance. + When set to `false`, the PHY operates in half-duplex mode, where data transmission and reception cannot occur simultaneously, + leading to a possible increase in data collisions and retransmissions, especially in high traffic conditions. + Selecting the appropriate duplex mode depends on network infrastructure, cable types, and the capabilities of the network devices involved in the connection. + + + enable-jumbo: + type: boolean + description: | + Specifies whether Jumbo Frames are enabled for the Ethernet device. Jumbo Frames are Ethernet frames with a payload greater than the standard maximum of 1500 bytes, + often up to 9000 bytes (9 KB). Enabling Jumbo Frames (`true`) can significantly increase data transfer efficiency by reducing the number of frames needed to transmit large amounts of data, + thereby decreasing CPU usage, increasing throughput, and improving network performance. + However, all devices in the network path must support Jumbo Frames to avoid fragmentation or dropped packets. + Disabling this feature (`false`) restricts the Ethernet frames to standard sizes, ensuring compatibility with network devices that do not support Jumbo Frames. + + + enable-ucast-hash: + type: boolean + description: | + Determines whether unicast hash filtering is enabled for the Ethernet device. + When activated (`true`), this feature allows the network interface to filter incoming unicast packets based on a hash function applied to the destination MAC address. + This mechanism is particularly useful in managing network traffic by ensuring that the Ethernet device processes only those unicast packets that match its hash criteria, + effectively reducing unnecessary packet processing and improving overall network efficiency. + This is beneficial in environments with high traffic levels or when the network interface is part of a larger, segmented network setup. + Disabling this feature (`false`) means the device will not use hash-based filtering for incoming unicast frames, + potentially leading to increased processing of irrelevant packets. + + + copy-all-frames: + type: boolean + description: | + Controls whether the Ethernet device is set to copy all incoming frames to system memory, + regardless of their destination MAC address. When enabled (`true`), + this feature instructs the device to pass all observed frames to the higher layers of the network stack, + effectively putting the network interface in a promiscuous mode. This mode is essential for network monitoring, + packet sniffing, and debugging tasks, where it's necessary to examine all traffic passing through the network segment the device is attached to. + However, it can lead to increased processing overhead due to the higher volume of data being passed up the stack. When disabled (`false`), + the device filters incoming frames, processing only those addressed to it or broadcast/multicast frames, + depending on its configuration, which is the normal operation mode for most network interfaces. + + + disable-reject-fcs-crc-errors: + type: boolean + description: | + Optional feature flag - Disable rejection of FCS/CRC errors. + When set, frames with FCS/CRC errors will not be rejected. FCS error + statistics will still be collected for frames with bad FCS and FCS + status will be recorded in the frame's DMA descriptor. This option + should not be activated for normal operation. + + enable-mcast-hash: + type: boolean + description: | + Enables multicast hash filtering for the Ethernet device. + When set to `true`, this feature allows the network interface to utilize a hash function on the destination MAC address of incoming multicast packets to determine if they should be passed to the system for processing. + This targeted approach helps manage multicast traffic more efficiently by ensuring the device processes only those multicast packets that match predefined criteria, + reducing unnecessary data processing and enhancing network throughput. This is especially beneficial in environments with substantial multicast traffic, such as multimedia streaming or multicast group communications. When disabled (`false`), + the device may not use hash-based filtering for multicast frames, which could result in increased processing of multicast packets that are not of interest to the receiving system. + + + handle-rx-in-isr: + type: boolean + description: | + Moves the handling of the frame received interrupt including the + transfer of packet data from the DMA to network packet buffers and + the subsequent propagation of the received packets to the network + stack into the context of the ISR. Due to the unpredictability of + the runtime of the ISR whenever large amounts of data are received, + handling of the RX interrupt is normally deferred to the context + of the system work queue. + + + handle-tx-in-workq: + type: boolean + description: | + Moves the handling of the frame transmission done interrupt into the + context of the system work queue. By default, TX done handling is per- + formed in the context of the ISR, as it only involves a limited number + of memory accesses. This option CAN NOT be used if any component ex- + ists within the current system setup that triggers the transmission + of packets from within the context of the system work queue! + + + rx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the RX buffer descriptor + ring. Must be <= 255. + + + rx-buffer-size: + type: int + required: true + description: | + The size of each receive data buffer, must be a multiple of 8, highest + valid value is 16320, values less than 64 are not really useful. + + + tx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the TX buffer descriptor + ring. Must be <= 255. + + tx-buffer-size: + type: int + required: true + description: | + The size of each transmit data buffer, highest valid value is 16380, + values less than 64 are not really useful. + diff --git a/dts/bindings/ethernet/phytium,xmac_v2.yaml b/dts/bindings/ethernet/phytium,xmac_v2.yaml new file mode 100644 index 0000000000000000000000000000000000000000..696de182b37eb408be411872370c38af7298180f --- /dev/null +++ b/dts/bindings/ethernet/phytium,xmac_v2.yaml @@ -0,0 +1,243 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium xmac v2 Ethernet controller + +compatible: "phytium,xmac_v2" + +include: ethernet-controller.yaml + +properties: + reg: + required: true + + mac-regs: + type: array + required: true + description: MAC register address range + + msg-regs: + type: array + required: true + description: Message register address range + + interrupts: + required: true + + clock-frequency: + type: int + required: true + description: | + Specifies the base clock frequency from which the XMAC's TX clock + frequency . + + phy-poll-interval: + type: int + required: true + description: | + PHY status polling interval in milliseconds for a driver instance + managing an associated PHY. + + phy-speed: + type: int + required: true + description: | + Nominal link speed. If no PHY is managed by an instance of this driver, + the respective controller will be configured to match the link speed + specified here. If a PHY is managed by the driver, advertisement of + the link speed specified here will be requested. If the optional pro- + perty advertise-lower-link-speeds is set, advertisement of the link + speed specified here plus any valid link speed below this value will + be requested. + enum: + - 10 + - 100 + - 1000 + - 10000 + + + interface-mode: + type: int + required: true + description: | + Specifies the interface mode for the Xmac. Each mode corresponds to a different type of media-independent interface that determines how the Ethernet PHY is connected to the MAC. The available modes are: + - 0: SGMII (Serial Gigabit Media Independent Interface), a serial version of the Gigabit Media Independent Interface that is used for Gigabit Ethernet connections. + - 1: RMII (Reduced Media Independent Interface), a reduced version of the Media Independent Interface designed for 10/100Mbps Ethernet connections with a reduced number of signal lines. + - 2: RGMII (Reduced Gigabit Media Independent Interface), a version of the Gigabit Media Independent Interface designed for 10/100/1000Mbps Ethernet connections with a reduced number of signal lines. + - 3: USXGMII (Universal Serial 10 Gigabit Media Independent Interface), a serial interface designed for speeds beyond 1Gbps, supporting a range of speeds up to 10Gbps over a single pair of copper or optical fiber. + enum: + - 0 + - 1 + - 2 + - 3 + + + + dma-brust-length: + type: int + required: true + description: | + Defines the burst length for DMA (Direct Memory Access) operations in the Xmac driver. + The burst length specifies the maximum number of words the DMA controller can transfer in a single burst. + Adjusting this parameter can impact the efficiency of data transfers between the Ethernet MAC and the system memory, + potentially affecting overall throughput and latency. A value of 16 indicates that the DMA controller is configured to transfer up to 16 words in a single burst. + Choosing the optimal burst length depends on the specific characteristics of the system, including the DMA controller's capabilities and the memory system's response to burst accesses. + enum: + - 16 + + + max-queue-num: + type: int + required: true + description: | + Specifies the maximum number of queue slots available for managing Ethernet frames in the Xmac driver. + This parameter determines the capacity of the driver to handle multiple Ethernet frames concurrently, + which can influence the efficiency of packet processing, especially under high network traffic conditions. + A value of 1 indicates that the driver is configured to manage Ethernet frames using a single queue. + This configuration is suitable for simpler network setups or systems with lower traffic demands. + Implementing multiple queues can be advantageous in systems that require high throughput and efficient traffic management, + but this comes at the cost of increased complexity in queue management. + enum: + - 1 + + + phy-autonegotiation: + type: boolean + description: | + Determines whether the PHY (Physical Layer Transceiver) should use autonegotiation to automatically select the speed and duplex mode of the Ethernet connection. + When enabled (`true`), the PHY will communicate with the link partner (typically a switch, router, or another network device) to determine the best mutual settings for speed (10/100/1000 Mbps) and duplex mode (half or full duplex). + This process ensures compatibility and optimizes the connection for the best possible performance. + When disabled (`false`), the PHY will not initiate or respond to autonegotiation attempts, and the speed and duplex mode must be manually configured to match the link partner's settings, potentially reducing flexibility and compatibility. + + + enable-fdx: + type: boolean + description: | + Indicates whether the PHY (Physical Layer Transceiver) should operate in full-duplex mode. + In full-duplex mode (`true`), the Ethernet connection supports simultaneous bi-directional data transmission, allowing data to be sent and received at the same time, + effectively doubling the potential throughput compared to half-duplex. + This mode is ideal for high-speed networks where data collisions are managed and can significantly enhance network performance. + When set to `false`, the PHY operates in half-duplex mode, where data transmission and reception cannot occur simultaneously, + leading to a possible increase in data collisions and retransmissions, especially in high traffic conditions. + Selecting the appropriate duplex mode depends on network infrastructure, cable types, and the capabilities of the network devices involved in the connection. + + + enable-jumbo: + type: boolean + description: | + Specifies whether Jumbo Frames are enabled for the Ethernet device. Jumbo Frames are Ethernet frames with a payload greater than the standard maximum of 1500 bytes, + often up to 9000 bytes (9 KB). Enabling Jumbo Frames (`true`) can significantly increase data transfer efficiency by reducing the number of frames needed to transmit large amounts of data, + thereby decreasing CPU usage, increasing throughput, and improving network performance. + However, all devices in the network path must support Jumbo Frames to avoid fragmentation or dropped packets. + Disabling this feature (`false`) restricts the Ethernet frames to standard sizes, ensuring compatibility with network devices that do not support Jumbo Frames. + + + enable-ucast-hash: + type: boolean + description: | + Determines whether unicast hash filtering is enabled for the Ethernet device. + When activated (`true`), this feature allows the network interface to filter incoming unicast packets based on a hash function applied to the destination MAC address. + This mechanism is particularly useful in managing network traffic by ensuring that the Ethernet device processes only those unicast packets that match its hash criteria, + effectively reducing unnecessary packet processing and improving overall network efficiency. + This is beneficial in environments with high traffic levels or when the network interface is part of a larger, segmented network setup. + Disabling this feature (`false`) means the device will not use hash-based filtering for incoming unicast frames, + potentially leading to increased processing of irrelevant packets. + + + copy-all-frames: + type: boolean + description: | + Controls whether the Ethernet device is set to copy all incoming frames to system memory, + regardless of their destination MAC address. When enabled (`true`), + this feature instructs the device to pass all observed frames to the higher layers of the network stack, + effectively putting the network interface in a promiscuous mode. This mode is essential for network monitoring, + packet sniffing, and debugging tasks, where it's necessary to examine all traffic passing through the network segment the device is attached to. + However, it can lead to increased processing overhead due to the higher volume of data being passed up the stack. When disabled (`false`), + the device filters incoming frames, processing only those addressed to it or broadcast/multicast frames, + depending on its configuration, which is the normal operation mode for most network interfaces. + + + disable-reject-fcs-crc-errors: + type: boolean + description: | + Optional feature flag - Disable rejection of FCS/CRC errors. + When set, frames with FCS/CRC errors will not be rejected. FCS error + statistics will still be collected for frames with bad FCS and FCS + status will be recorded in the frame's DMA descriptor. This option + should not be activated for normal operation. + + enable-mcast-hash: + type: boolean + description: | + Enables multicast hash filtering for the Ethernet device. + When set to `true`, this feature allows the network interface to utilize a hash function on the destination MAC address of incoming multicast packets to determine if they should be passed to the system for processing. + This targeted approach helps manage multicast traffic more efficiently by ensuring the device processes only those multicast packets that match predefined criteria, + reducing unnecessary data processing and enhancing network throughput. This is especially beneficial in environments with substantial multicast traffic, such as multimedia streaming or multicast group communications. When disabled (`false`), + the device may not use hash-based filtering for multicast frames, which could result in increased processing of multicast packets that are not of interest to the receiving system. + + + handle-rx-in-isr: + type: boolean + description: | + Moves the handling of the frame received interrupt including the + transfer of packet data from the DMA to network packet buffers and + the subsequent propagation of the received packets to the network + stack into the context of the ISR. Due to the unpredictability of + the runtime of the ISR whenever large amounts of data are received, + handling of the RX interrupt is normally deferred to the context + of the system work queue. + + + handle-tx-in-workq: + type: boolean + description: | + Moves the handling of the frame transmission done interrupt into the + context of the system work queue. By default, TX done handling is per- + formed in the context of the ISR, as it only involves a limited number + of memory accesses. This option CAN NOT be used if any component ex- + ists within the current system setup that triggers the transmission + of packets from within the context of the system work queue! + + + rx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the RX buffer descriptor + ring. Must be <= 255. + + + rx-buffer-size: + type: int + required: true + description: | + The size of each receive data buffer, must be a multiple of 8, highest + valid value is 16320, values less than 64 are not really useful. + + + tx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the TX buffer descriptor + ring. Must be <= 255. + + tx-buffer-size: + type: int + required: true + description: | + The size of each transmit data buffer, highest valid value is 16380, + values less than 64 are not really useful. + diff --git a/dts/bindings/pinctrl/phytium,pinctrl.yaml b/dts/bindings/pinctrl/phytium,pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3a2e5da838d3e9d2227fe1b473eaf659c3f7c16c --- /dev/null +++ b/dts/bindings/pinctrl/phytium,pinctrl.yaml @@ -0,0 +1,38 @@ + +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: | + Phytium pinctrl node + +compatible: "phytium,pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the Phytium + pin configuration. + + properties: + pinmux: + required: true + type: array + description: | + Phytium pin configuration. diff --git a/dts/bindings/sdhc/phytium,sdhc.yaml b/dts/bindings/sdhc/phytium,sdhc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..014ada1d64a23f05e7d883eb2a3e28634e29f767 --- /dev/null +++ b/dts/bindings/sdhc/phytium,sdhc.yaml @@ -0,0 +1,64 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: Phytium SDHC controller + +compatible: "phytium,sdhc" + +include: [sdhc.yaml] + +properties: + reg: + required: true + + pio-id: + type: int + + default: 0 + description: | + pio id + + pio-base: + type: int + required: true + + pio-length: + type: int + default: 0x1000 + description: | + pio length + + is-enable-irq: + type: int + default: 1 + description: | + enable irq + + data-timeout: + type: int + default: 0xF + description: | + Data timeout, as multiple of the SD clock. See DTOCV field of USDHC + + no-1-8-v: + type: boolean + description: | + When the external SD card circuit does not support 1.8V, add this + property to disable 1.8v card voltage of SD card controller. + + non-removeable: + type: boolean + description: | + The host controller is for non-remveable device, e.g. eMMC \ No newline at end of file diff --git a/dts/bindings/serial/arm,pl011.yaml b/dts/bindings/serial/arm,pl011.yaml index e823638ede0492eca7db306ab09f8e7fc8561a3c..80b4f2a7c18a78da20c173a93f2ecdebd6f308f9 100644 --- a/dts/bindings/serial/arm,pl011.yaml +++ b/dts/bindings/serial/arm,pl011.yaml @@ -10,3 +10,5 @@ properties: interrupts: required: true + + diff --git a/dts/bindings/serial/phytium,pl011.yaml b/dts/bindings/serial/phytium,pl011.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8b5804e7e4511ffc90c62b5c2428bd11773ea15d --- /dev/null +++ b/dts/bindings/serial/phytium,pl011.yaml @@ -0,0 +1,27 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +description: PHYTIUM PL011 UART + +compatible: "phytium,pl011" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index edf9c4ae82583b71212c4d33f2cbccd73923db5c..e524453a7adfc7be59d44d1297452bcae06b136d 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -11,6 +11,7 @@ # # zephyr-keep-sorted-start +phytium Phytium Technology 96boards 96Boards aaeon AAEON Technology Inc. abb ABB diff --git a/include/zephyr/arch/arm/arch.h b/include/zephyr/arch/arm/arch.h index 804e1d23dbdd51e999b1010306233a24c537f080..759df697f8341973e2325e29463a30dbb8baf000 100644 --- a/include/zephyr/arch/arm/arch.h +++ b/include/zephyr/arch/arm/arch.h @@ -43,7 +43,7 @@ #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #include #include -#if defined(CONFIG_AARCH32_ARMV8_R) +#if defined(CONFIG_AARCH32_ARMV8_R) || defined(CONFIG_CPU_AARCH32_ARMV8) #include #include #else diff --git a/include/zephyr/arch/arm/cortex_a_r/cpu.h b/include/zephyr/arch/arm/cortex_a_r/cpu.h index 13455fe6ac4bab304617b61a90782bf42b500da2..ccaf2b880e471a0d14b27b021361a8f938c6b350 100644 --- a/include/zephyr/arch/arm/cortex_a_r/cpu.h +++ b/include/zephyr/arch/arm/cortex_a_r/cpu.h @@ -85,7 +85,7 @@ #define ICC_SRE_EL3_EN_BIT BIT(3) /* MPIDR */ -#define MPIDR_AFFLVL_MASK (0xff) +#define MPIDR_AFFLVL_MASK (0xfff) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF1_SHIFT (8) diff --git a/include/zephyr/arch/arm64/lib_helpers.h b/include/zephyr/arch/arm64/lib_helpers.h index 0f3d9d563abe246080349b8824d49d4b6b7a5ee3..117c79a326c13f6c716839a69397bcfdfc10c699 100644 --- a/include/zephyr/arch/arm64/lib_helpers.h +++ b/include/zephyr/arch/arm64/lib_helpers.h @@ -62,6 +62,9 @@ MAKE_REG_HELPER(cnthps_ctl_el2); MAKE_REG_HELPER(cntv_ctl_el0) MAKE_REG_HELPER(cntv_cval_el0) MAKE_REG_HELPER(cntvct_el0); +MAKE_REG_HELPER(cntpct_el0); +MAKE_REG_HELPER(cnthp_cval_el2) +MAKE_REG_HELPER(cnthp_tval_el2) MAKE_REG_HELPER(cntvoff_el2); MAKE_REG_HELPER(currentel); MAKE_REG_HELPER(csselr_el1); diff --git a/include/zephyr/arch/arm64/timer.h b/include/zephyr/arch/arm64/timer.h index d8abba1c0e4efb6b942f10e7b64f2333e4ab46a7..8610ca956069f1ce2c660c051ce6c4658162605a 100644 --- a/include/zephyr/arch/arm64/timer.h +++ b/include/zephyr/arch/arm64/timer.h @@ -19,7 +19,11 @@ extern "C" { #endif +#ifndef CONFIG_USE_EL2 #define ARM_ARCH_TIMER_IRQ ARM_TIMER_VIRTUAL_IRQ +#else +#define ARM_ARCH_TIMER_IRQ ARM_TIMER_HYP_IRQ +#endif #define ARM_ARCH_TIMER_PRIO ARM_TIMER_VIRTUAL_PRIO #define ARM_ARCH_TIMER_FLAGS ARM_TIMER_VIRTUAL_FLAGS @@ -36,37 +40,52 @@ static ALWAYS_INLINE void arm_arch_timer_init(void) static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val) { +#ifndef CONFIG_USE_EL2 write_cntv_cval_el0(val); +#else + write_cnthp_cval_el2(val); +#endif } static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable) { uint64_t cntv_ctl; - +#ifndef CONFIG_USE_EL2 cntv_ctl = read_cntv_ctl_el0(); +#else + cntv_ctl = read_cnthp_ctl_el2(); +#endif if (enable) { cntv_ctl |= CNTV_CTL_ENABLE_BIT; } else { cntv_ctl &= ~CNTV_CTL_ENABLE_BIT; } - +#ifndef CONFIG_USE_EL2 write_cntv_ctl_el0(cntv_ctl); +#else + write_cnthp_ctl_el2(cntv_ctl); +#endif } static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask) { uint64_t cntv_ctl; - +#ifndef CONFIG_USE_EL2 cntv_ctl = read_cntv_ctl_el0(); - +#else + cntv_ctl = read_cnthp_ctl_el2(); +#endif if (mask) { cntv_ctl |= CNTV_CTL_IMASK_BIT; } else { cntv_ctl &= ~CNTV_CTL_IMASK_BIT; } - +#ifndef CONFIG_USE_EL2 write_cntv_ctl_el0(cntv_ctl); +#else + write_cnthp_ctl_el2(cntv_ctl); +#endif } static ALWAYS_INLINE uint64_t arm_arch_timer_count(void) diff --git a/include/zephyr/dt-bindings/pinctrl/phytium-pd2308-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/phytium-pd2308-pinctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..d18cf773f1653f7094d9d00628260df438b8fb74 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/phytium-pd2308-pinctrl.h @@ -0,0 +1,226 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ + +#define FIOPAD_C5_REG0_OFFSET 0x0018U +#define FIOPAD_E5_REG0_OFFSET 0x001CU + +#define FIOPAD_E3_REG0_OFFSET 0x0020U +#define FIOPAD_L5_REG0_OFFSET 0x0024U +#define FIOPAD_J5_REG0_OFFSET 0x0028U +#define FIOPAD_L3_REG0_OFFSET 0x002CU + +#define FIOPAD_N1_REG0_OFFSET 0x0030U +#define FIOPAD_L1_REG0_OFFSET 0x0034U +#define FIOPAD_J1_REG0_OFFSET 0x0038U +#define FIOPAD_N5_REG0_OFFSET 0x003CU + +#define FIOPAD_CH19_REG0_OFFSET 0x0040U +#define FIOPAD_CF19_REG0_OFFSET 0x0044U +#define FIOPAD_G3_REG0_OFFSET 0x0048U +#define FIOPAD_G1_REG0_OFFSET 0x004CU + +#define FIOPAD_G5_REG0_OFFSET 0x0050U +#define FIOPAD_CB19_REG0_OFFSET 0x0054U +#define FIOPAD_CB21_REG0_OFFSET 0x0058U +#define FIOPAD_BY19_REG0_OFFSET 0x005CU + +#define FIOPAD_U13_REG0_OFFSET 0x0060U +#define FIOPAD_U15_REG0_OFFSET 0x0064U +#define FIOPAD_AA7_REG0_OFFSET 0x0068U +#define FIOPAD_AA9_REG0_OFFSET 0x006CU + +#define FIOPAD_AA13_REG0_OFFSET 0x0070U +#define FIOPAD_AA11_REG0_OFFSET 0x0074U +#define FIOPAD_AA15_REG0_OFFSET 0x0078U +#define FIOPAD_W11_REG0_OFFSET 0x007CU + +#define FIOPAD_W7_REG0_OFFSET 0x0080U +#define FIOPAD_U11_REG0_OFFSET 0x0084U +#define FIOPAD_U9_REG0_OFFSET 0x0088U +#define FIOPAD_U3_REG0_OFFSET 0x008CU + +#define FIOPAD_U1_REG0_OFFSET 0x0090U +#define FIOPAD_CM43_REG0_OFFSET 0x0094U +#define FIOPAD_CP45_REG0_OFFSET 0x0098U +#define FIOPAD_CH21_REG0_OFFSET 0x009CU + +#define FIOPAD_CK19_REG0_OFFSET 0x00A0U +#define FIOPAD_BT67_REG0_OFFSET 0x00A4U +#define FIOPAD_BP67_REG0_OFFSET 0x00A8U +#define FIOPAD_BV63_REG0_OFFSET 0x00ACU + +#define FIOPAD_BT63_REG0_OFFSET 0x00B0U +#define FIOPAD_AN17_REG0_OFFSET 0x00B4U +#define FIOPAD_AR17_REG0_OFFSET 0x00B8U +#define FIOPAD_AR15_REG0_OFFSET 0x00BCU + +#define FIOPAD_AN15_REG0_OFFSET 0x00C0U +#define FIOPAD_AJ19_REG0_OFFSET 0x00C4U +#define FIOPAD_AN19_REG0_OFFSET 0x00C8U +#define FIOPAD_AJ15_REG0_OFFSET 0x00CCU + +#define FIOPAD_AG21_REG0_OFFSET 0x00D0U +#define FIOPAD_AJ13_REG0_OFFSET 0x00D4U +#define FIOPAD_AJ11_REG0_OFFSET 0x00D8U +#define FIOPAD_AN21_REG0_OFFSET 0x00DCU + +#define FIOPAD_AC5_REG0_OFFSET 0x00E0U +#define FIOPAD_AE1_REG0_OFFSET 0x00E4U +#define FIOPAD_AE3_REG0_OFFSET 0x00E8U +#define FIOPAD_AC3_REG0_OFFSET 0x00ECU + +#define FIOPAD_AR19_REG0_OFFSET 0x00F0U +#define FIOPAD_BM21_REG0_OFFSET 0x00F4U +#define FIOPAD_BK19_REG0_OFFSET 0x00F8U +#define FIOPAD_BK21_REG0_OFFSET 0x00FCU + +#define FIOPAD_BM19_REG0_OFFSET 0x0100U +#define FIOPAD_BP21_REG0_OFFSET 0x0104U +#define FIOPAD_BP19_REG0_OFFSET 0x0108U +#define FIOPAD_BV19_REG0_OFFSET 0x010CU + +#define FIOPAD_BV12_REG0_OFFSET 0x0110U +#define FIOPAD_CF67_REG0_OFFSET 0x0114U +#define FIOPAD_CD67_REG0_OFFSET 0x0118U +#define FIOPAD_BY65_REG0_OFFSET 0x011CU + +#define FIOPAD_BY67_REG0_OFFSET 0x0120U +#define FIOPAD_CB67_REG0_OFFSET 0x0124U +#define FIOPAD_BV65_REG0_OFFSET 0x0128U +#define FIOPAD_BV67_REG0_OFFSET 0x012CU + +#define FIOPAD_BY63_REG0_OFFSET 0x0130U +#define FIOPAD_CB63_REG0_OFFSET 0x0134U +#define FIOPAD_CD63_REG0_OFFSET 0x0138U +#define FIOPAD_W5_REG0_OFFSET 0x013CU + +#define FIOPAD_U5_REG0_OFFSET 0x0140U +#define FIOPAD_W3_REG0_OFFSET 0x0144U +#define FIOPAD_AC7_REG0_OFFSET 0x0148U +#define FIOPAD_W1_REG0_OFFSET 0x014CU + +#define FIOPAD_AA5_REG0_OFFSET 0x0150U +#define FIOPAD_AA1_REG0_OFFSET 0x0154U +#define FIOPAD_AC1_REG0_OFFSET 0x0158U +#define FIOPAD_BM63_REG0_OFFSET 0x015CU + +#define FIOPAD_BP63_REG0_OFFSET 0x0160U +#define FIOPAD_CM47_REG0_OFFSET 0x0164U +#define FIOPAD_CK47_REG0_OFFSET 0x0168U +#define FIOPAD_AG13_REG0_OFFSET 0x016CU + +#define FIOPAD_AG11_REG0_OFFSET 0x0170U +#define FIOPAD_AL15_REG0_OFFSET 0x0174U +#define FIOPAD_AJ17_REG0_OFFSET 0x0178U +#define FIOPAD_AC15_REG0_OFFSET 0x017CU + +#define FIOPAD_AC9_REG0_OFFSET 0x0180U +#define FIOPAD_AC11_REG0_OFFSET 0x0184U +#define FIOPAD_AE13_REG0_OFFSET 0x0188U +#define FIOPAD_AE11_REG0_OFFSET 0x018CU + +#define FIOPAD_CD65_REG0_OFFSET 0x0190U +#define FIOPAD_CF63_REG0_OFFSET 0x0194U +#define FIOPAD_CH63_REG0_OFFSET 0x0198U +#define FIOPAD_CH65_REG0_OFFSET 0x019CU + +#define FIOPAD_CH67_REG0_OFFSET 0x01A0U +#define FIOPAD_AE17_REG0_OFFSET 0x01A4U +#define FIOPAD_CF65_REG0_OFFSET 0x01A8U +#define FIOPAD_AA19_REG0_OFFSET 0x01ACU + +#define FIOPAD_CE61_REG0_OFFSET 0x01B0U +#define FIOPAD_AC19_REG0_OFFSET 0x01B4U +#define FIOPAD_AA17_REG0_OFFSET 0x01B8U +#define FIOPAD_W13_REG0_OFFSET 0x01BCU + +#define FIOPAD_AG15_REG0_OFFSET 0x01C0U +#define FIOPAD_AE21_REG0_OFFSET 0x01C4U +#define FIOPAD_CM45_REG0_OFFSET 0x01C8U +#define FIOPAD_CK45_REG0_OFFSET 0x01CCU + +#define FIOPAD_BM65_REG0_OFFSET 0x01D0U +#define FIOPAD_BP65_REG0_OFFSET 0x01D4U + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_C5_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_BP65_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_CK19_REG1_OFFSET 0x10A0U +#define FIOPAD_BT67_REG1_OFFSET 0x10A4U +#define FIOPAD_BP67_REG1_OFFSET 0x10A8U +#define FIOPAD_BV63_REG1_OFFSET 0x10ACU + +#define FIOPAD_BT63_REG1_OFFSET 0x10B0U +#define FIOPAD_AN17_REG1_OFFSET 0x10B4U +#define FIOPAD_AR17_REG1_OFFSET 0x10B8U +#define FIOPAD_AR15_REG1_OFFSET 0x10BCU + +#define FIOPAD_AN15_REG1_OFFSET 0x10C0U +#define FIOPAD_AJ19_REG1_OFFSET 0x10C4U +#define FIOPAD_AN19_REG1_OFFSET 0x10C8U +#define FIOPAD_AJ15_REG1_OFFSET 0x10CCU + +#define FIOPAD_AG21_REG1_OFFSET 0x10D0U +#define FIOPAD_AJ13_REG1_OFFSET 0x10D4U +#define FIOPAD_AJ11_REG1_OFFSET 0x10D8U +#define FIOPAD_AN21_REG1_OFFSET 0x10DCU + +#define FIOPAD_AE1_REG1_OFFSET 0x10E4U +#define FIOPAD_AE3_REG1_OFFSET 0x10E8U +#define FIOPAD_AC3_REG1_OFFSET 0x10ECU + +#define FIOPAD_AR19_REG1_OFFSET 0x10F0U +#define FIOPAD_BM21_REG1_OFFSET 0x10F4U +#define FIOPAD_BK19_REG1_OFFSET 0x10F8U +#define FIOPAD_BK21_REG1_OFFSET 0x10FCU + +#define FIOPAD_BM19_REG1_OFFSET 0x1100U +#define FIOPAD_BP21_REG1_OFFSET 0x1104U +#define FIOPAD_BP19_REG1_OFFSET 0x1108U +#define FIOPAD_BV19_REG1_OFFSET 0x110CU + +#define FIOPAD_BV21_REG1_OFFSET 0x1110U +#define FIOPAD_CF67_REG1_OFFSET 0x1114U +#define FIOPAD_CD67_REG1_OFFSET 0x1118U +#define FIOPAD_BY65_REG1_OFFSET 0x111CU + +#define FIOPAD_BY67_REG1_OFFSET 0x1120U +#define FIOPAD_CB67_REG1_OFFSET 0x1124U +#define FIOPAD_BV65_REG1_OFFSET 0x1128U + +#define FIOPAD_CD65_REG1_OFFSET 0x1190U +#define FIOPAD_CF63_REG1_OFFSET 0x1194U +#define FIOPAD_CH63_REG1_OFFSET 0x1198U +#define FIOPAD_CH65_REG1_OFFSET 0x119CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_CK19_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_CH65_REG1_OFFSET + +#define FIOPAD_FUNC0 0x0 +#define FIOPAD_FUNC1 0x1 +#define FIOPAD_FUNC2 0x2 +#define FIOPAD_FUNC3 0x3 +#define FIOPAD_FUNC4 0x4 +#define FIOPAD_FUNC5 0x5 +#define FIOPAD_FUNC6 0x6 +#define FIOPAD_FUNC7 0x7 + +#define PHYTIUM_PINMUX(pin_reg_offset, func_num) (pin_reg_offset) (func_num) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/phytium-pd2408-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/phytium-pd2408-pinctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..f1b7c9935d57db83415ff684aad253183b21c4d2 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/phytium-pd2408-pinctrl.h @@ -0,0 +1,168 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_C7_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_T2_REG0_OFFSET + +#define FIOPAD_C7_REG0_OFFSET 0x0018U +#define FIOPAD_B4_REG0_OFFSET 0x0024U +#define FIOPAD_B6_REG0_OFFSET 0x0028U +#define FIOPAD_A5_REG0_OFFSET 0x002CU +#define FIOPAD_C3_REG0_OFFSET 0x0030U +#define FIOPAD_B8_REG0_OFFSET 0x0034U +#define FIOPAD_E1_REG0_OFFSET 0x0038U +#define FIOPAD_R3_REG0_OFFSET 0x003CU +#define FIOPAD_P2_REG0_OFFSET 0x0040U +#define FIOPAD_A9_REG0_OFFSET 0x0044U +#define FIOPAD_C9_REG0_OFFSET 0x0048U +#define FIOPAD_F10_REG0_OFFSET 0x004CU +#define FIOPAD_AD6_REG0_OFFSET 0x0050U +#define FIOPAD_AK6_REG0_OFFSET 0x0054U +#define FIOPAD_Y8_REG0_OFFSET 0x0058U +#define FIOPAD_AJ5_REG0_OFFSET 0x005CU +#define FIOPAD_AH6_REG0_OFFSET 0x0060U +#define FIOPAD_AC5_REG0_OFFSET 0x0064U +#define FIOPAD_AB6_REG0_OFFSET 0x0068U +#define FIOPAD_AF6_REG0_OFFSET 0x006CU +#define FIOPAD_AB8_REG0_OFFSET 0x0070U +#define FIOPAD_AA5_REG0_OFFSET 0x0074U +#define FIOPAD_V6_REG0_OFFSET 0x0078U +#define FIOPAD_W5_REG0_OFFSET 0x007CU +#define FIOPAD_Y6_REG0_OFFSET 0x0080U +#define FIOPAD_W3_REG0_OFFSET 0x0084U +#define FIOPAD_U5_REG0_OFFSET 0x0088U +#define FIOPAD_T8_REG0_OFFSET 0x008CU +#define FIOPAD_V8_REG0_OFFSET 0x0090U +#define FIOPAD_P8_REG0_OFFSET 0x0094U +#define FIOPAD_M8_REG0_OFFSET 0x0098U +#define FIOPAD_AE5_REG0_OFFSET 0x009CU +#define FIOPAD_AG5_REG0_OFFSET 0x00A0U +#define FIOPAD_J13_REG0_OFFSET 0x00A4U +#define FIOPAD_L13_REG0_OFFSET 0x00A8U +#define FIOPAD_D10_REG0_OFFSET 0x00ACU +#define FIOPAD_E9_REG0_OFFSET 0x00B0U +#define FIOPAD_BL19_REG0_OFFSET 0x00B4U +#define FIOPAD_BK18_REG0_OFFSET 0x00B8U +#define FIOPAD_BL15_REG0_OFFSET 0x00BCU +#define FIOPAD_BK16_REG0_OFFSET 0x00C0U +#define FIOPAD_BL13_REG0_OFFSET 0x00C4U +#define FIOPAD_BK14_REG0_OFFSET 0x00C8U +#define FIOPAD_J1_REG0_OFFSET 0x00CCU +#define FIOPAD_H2_REG0_OFFSET 0x00D0U +#define FIOPAD_E3_REG0_OFFSET 0x00D4U +#define FIOPAD_F2_REG0_OFFSET 0x00D8U +#define FIOPAD_G3_REG0_OFFSET 0x00DCU +#define FIOPAD_E5_REG0_OFFSET 0x00E0U +#define FIOPAD_F6_REG0_OFFSET 0x00E4U +#define FIOPAD_E7_REG0_OFFSET 0x00E8U +#define FIOPAD_F8_REG0_OFFSET 0x00ECU +#define FIOPAD_N3_REG0_OFFSET 0x00F0U +#define FIOPAD_N1_REG0_OFFSET 0x00F4U +#define FIOPAD_M2_REG0_OFFSET 0x00F8U +#define FIOPAD_K2_REG0_OFFSET 0x00FCU +#define FIOPAD_K8_REG0_OFFSET 0x0100U +#define FIOPAD_M6_REG0_OFFSET 0x0104U +#define FIOPAD_H6_REG0_OFFSET 0x0108U +#define FIOPAD_K6_REG0_OFFSET 0x010CU +#define FIOPAD_J5_REG0_OFFSET 0x0110U +#define FIOPAD_J3_REG0_OFFSET 0x0114U +#define FIOPAD_G5_REG0_OFFSET 0x0118U +#define FIOPAD_L5_REG0_OFFSET 0x011CU +#define FIOPAD_L3_REG0_OFFSET 0x0120U +#define FIOPAD_AP4_REG0_OFFSET 0x0124U +#define FIOPAD_AE1_REG0_OFFSET 0x0128U +#define FIOPAD_AG3_REG0_OFFSET 0x012CU +#define FIOPAD_AJ3_REG0_OFFSET 0x0130U +#define FIOPAD_AD2_REG0_OFFSET 0x0134U +#define FIOPAD_AM4_REG0_OFFSET 0x0138U +#define FIOPAD_AR5_REG0_OFFSET 0x013CU +#define FIOPAD_AT6_REG0_OFFSET 0x0140U +#define FIOPAD_AC3_REG0_OFFSET 0x0144U +#define FIOPAD_AE3_REG0_OFFSET 0x0148U +#define FIOPAD_AF2_REG0_OFFSET 0x014CU +#define FIOPAD_AH2_REG0_OFFSET 0x0150U +#define FIOPAD_AJ1_REG0_OFFSET 0x0154U +#define FIOPAD_AK2_REG0_OFFSET 0x0158U +#define FIOPAD_BM12_REG0_OFFSET 0x015CU +#define FIOPAD_BM10_REG0_OFFSET 0x0160U +#define FIOPAD_BK12_REG0_OFFSET 0x0164U +#define FIOPAD_BL11_REG0_OFFSET 0x0168U +#define FIOPAD_BK20_REG0_OFFSET 0x016CU +#define FIOPAD_BL21_REG0_OFFSET 0x0170U +#define FIOPAD_BK22_REG0_OFFSET 0x0174U +#define FIOPAD_BL23_REG0_OFFSET 0x0178U +#define FIOPAD_BK24_REG0_OFFSET 0x017CU +#define FIOPAD_BL25_REG0_OFFSET 0x0180U +#define FIOPAD_AA3_REG0_OFFSET 0x0184U +#define FIOPAD_Y2_REG0_OFFSET 0x0188U +#define FIOPAD_V2_REG0_OFFSET 0x018CU +#define FIOPAD_AA1_REG0_OFFSET 0x0190U +#define FIOPAD_AB2_REG0_OFFSET 0x0194U +#define FIOPAD_T2_REG0_OFFSET 0x0198U + +/* register offset of iopad delay */ + +#define FIOPAD_C7_REG1_OFFSET 0x1018U +#define FIOPAD_B4_REG1_OFFSET 0x1024U +#define FIOPAD_B6_REG1_OFFSET 0x1028U +#define FIOPAD_D10_REG1_OFFSET 0x10ACU +#define FIOPAD_E9_REG1_OFFSET 0x10B0U +#define FIOPAD_J1_REG1_OFFSET 0x10CCU +#define FIOPAD_H2_REG1_OFFSET 0x10D0U +#define FIOPAD_E3_REG1_OFFSET 0x10D4U +#define FIOPAD_F2_REG1_OFFSET 0x10D8U +#define FIOPAD_G3_REG1_OFFSET 0x10DCU +#define FIOPAD_E5_REG1_OFFSET 0x10E0U +#define FIOPAD_F6_REG1_OFFSET 0x10E4U +#define FIOPAD_E7_REG1_OFFSET 0x10E8U +#define FIOPAD_K8_REG1_OFFSET 0x1100U +#define FIOPAD_M6_REG1_OFFSET 0x1104U +#define FIOPAD_H6_REG1_OFFSET 0x1108U +#define FIOPAD_K6_REG1_OFFSET 0x110CU +#define FIOPAD_J5_REG1_OFFSET 0x1110U +#define FIOPAD_J3_REG1_OFFSET 0x1114U +#define FIOPAD_G5_REG1_OFFSET 0x1118U +#define FIOPAD_L5_REG1_OFFSET 0x111CU +#define FIOPAD_L3_REG1_OFFSET 0x1120U +#define FIOPAD_AP4_REG1_OFFSET 0x1124U +#define FIOPAD_AE1_REG1_OFFSET 0x1128U +#define FIOPAD_AG3_REG1_OFFSET 0x112CU +#define FIOPAD_AJ3_REG1_OFFSET 0x1130U +#define FIOPAD_AD2_REG1_OFFSET 0x1134U +#define FIOPAD_AM4_REG1_OFFSET 0x1138U +#define FIOPAD_AE3_REG1_OFFSET 0x1148U +#define FIOPAD_AF2_REG1_OFFSET 0x114CU +#define FIOPAD_AH2_REG1_OFFSET 0x1150U +#define FIOPAD_AJ1_REG1_OFFSET 0x1154U + + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_C7_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_AJ1_REG1_OFFSET + +#define FIOPAD_FUNC0 0x0 +#define FIOPAD_FUNC1 0x1 +#define FIOPAD_FUNC2 0x2 +#define FIOPAD_FUNC3 0x3 +#define FIOPAD_FUNC4 0x4 +#define FIOPAD_FUNC5 0x5 +#define FIOPAD_FUNC6 0x6 +#define FIOPAD_FUNC7 0x7 + +#define PHYTIUM_PINMUX(pin_reg_offset, func_num) (pin_reg_offset) (func_num) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/phytium-pe2202-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/phytium-pe2202-pinctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..3f6f0f7ede3c44a5fd58a66edce2c534530662cd --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/phytium-pe2202-pinctrl.h @@ -0,0 +1,278 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ + +#define FIOPAD_AN55_REG0_OFFSET 0x0000U +#define FIOPAD_AW43_REG0_OFFSET 0x0004U +#define FIOPAD_AR51_REG0_OFFSET 0x0020U +#define FIOPAD_AJ51_REG0_OFFSET 0x0024U +#define FIOPAD_AL51_REG0_OFFSET 0x0028U +#define FIOPAD_AL49_REG0_OFFSET 0x002CU +#define FIOPAD_AN47_REG0_OFFSET 0x0030U +#define FIOPAD_AR47_REG0_OFFSET 0x0034U +#define FIOPAD_BA53_REG0_OFFSET 0x0038U +#define FIOPAD_BA55_REG0_OFFSET 0x003CU +#define FIOPAD_AW53_REG0_OFFSET 0x0040U +#define FIOPAD_AW55_REG0_OFFSET 0x0044U +#define FIOPAD_AU51_REG0_OFFSET 0x0048U +#define FIOPAD_AN53_REG0_OFFSET 0x004CU +#define FIOPAD_AL55_REG0_OFFSET 0x0050U +#define FIOPAD_AJ55_REG0_OFFSET 0x0054U +#define FIOPAD_AJ53_REG0_OFFSET 0x0058U +#define FIOPAD_AG55_REG0_OFFSET 0x005CU +#define FIOPAD_AG53_REG0_OFFSET 0x0060U +#define FIOPAD_AE55_REG0_OFFSET 0x0064U +#define FIOPAD_AC55_REG0_OFFSET 0x0068U +#define FIOPAD_AC53_REG0_OFFSET 0x006CU +#define FIOPAD_AR45_REG0_OFFSET 0x0070U +#define FIOPAD_BA51_REG0_OFFSET 0x0074U +#define FIOPAD_BA49_REG0_OFFSET 0x0078U +#define FIOPAD_AR55_REG0_OFFSET 0x007CU +#define FIOPAD_AU55_REG0_OFFSET 0x0080U +#define FIOPAD_AR53_REG0_OFFSET 0x0084U +#define FIOPAD_BA45_REG0_OFFSET 0x0088U +#define FIOPAD_AW51_REG0_OFFSET 0x008CU +#define FIOPAD_A31_REG0_OFFSET 0x0090U +#define FIOPAD_R53_REG0_OFFSET 0x0094U +#define FIOPAD_R55_REG0_OFFSET 0x0098U +#define FIOPAD_U55_REG0_OFFSET 0x009CU +#define FIOPAD_W55_REG0_OFFSET 0x00A0U +#define FIOPAD_U53_REG0_OFFSET 0x00A4U +#define FIOPAD_AA53_REG0_OFFSET 0x00A8U +#define FIOPAD_AA55_REG0_OFFSET 0x00ACU +#define FIOPAD_AW47_REG0_OFFSET 0x00B0U +#define FIOPAD_AU47_REG0_OFFSET 0x00B4U +#define FIOPAD_A35_REG0_OFFSET 0x00B8U +#define FIOPAD_C35_REG0_OFFSET 0x00BCU +#define FIOPAD_C33_REG0_OFFSET 0x00C0U +#define FIOPAD_A33_REG0_OFFSET 0x00C4U +#define FIOPAD_A37_REG0_OFFSET 0x00C8U +#define FIOPAD_A39_REG0_OFFSET 0x00CCU +#define FIOPAD_A41_REG0_OFFSET 0x00D0U +#define FIOPAD_C41_REG0_OFFSET 0x00D4U +#define FIOPAD_A43_REG0_OFFSET 0x00D8U +#define FIOPAD_A45_REG0_OFFSET 0x00DCU +#define FIOPAD_C45_REG0_OFFSET 0x00E0U +#define FIOPAD_A47_REG0_OFFSET 0x00E4U +#define FIOPAD_A29_REG0_OFFSET 0x00E8U +#define FIOPAD_C29_REG0_OFFSET 0x00ECU +#define FIOPAD_C27_REG0_OFFSET 0x00F0U +#define FIOPAD_A27_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U +#define FIOPAD_AL45_REG0_OFFSET 0x00FCU +#define FIOPAD_AL43_REG0_OFFSET 0x0100U +#define FIOPAD_AN45_REG0_OFFSET 0x0104U +#define FIOPAD_AG47_REG0_OFFSET 0x0108U +#define FIOPAD_AJ47_REG0_OFFSET 0x010CU +#define FIOPAD_AG45_REG0_OFFSET 0x0110U +#define FIOPAD_AE51_REG0_OFFSET 0x0114U +#define FIOPAD_AE49_REG0_OFFSET 0x0118U +#define FIOPAD_AG51_REG0_OFFSET 0x011CU +#define FIOPAD_AJ45_REG0_OFFSET 0x0120U +#define FIOPAD_AC51_REG0_OFFSET 0x0124U +#define FIOPAD_AC49_REG0_OFFSET 0x0128U +#define FIOPAD_AE47_REG0_OFFSET 0x012CU +#define FIOPAD_W47_REG0_OFFSET 0x0130U +#define FIOPAD_W51_REG0_OFFSET 0x0134U +#define FIOPAD_W49_REG0_OFFSET 0x0138U +#define FIOPAD_U51_REG0_OFFSET 0x013CU +#define FIOPAD_U49_REG0_OFFSET 0x0140U +#define FIOPAD_AE45_REG0_OFFSET 0x0144U +#define FIOPAD_AC45_REG0_OFFSET 0x0148U +#define FIOPAD_AE43_REG0_OFFSET 0x014CU +#define FIOPAD_AA43_REG0_OFFSET 0x0150U +#define FIOPAD_AA45_REG0_OFFSET 0x0154U +#define FIOPAD_W45_REG0_OFFSET 0x0158U +#define FIOPAD_AA47_REG0_OFFSET 0x015CU +#define FIOPAD_U45_REG0_OFFSET 0x0160U +#define FIOPAD_G55_REG0_OFFSET 0x0164U +#define FIOPAD_J55_REG0_OFFSET 0x0168U +#define FIOPAD_L53_REG0_OFFSET 0x016CU +#define FIOPAD_C55_REG0_OFFSET 0x0170U +#define FIOPAD_E55_REG0_OFFSET 0x0174U +#define FIOPAD_J53_REG0_OFFSET 0x0178U +#define FIOPAD_L55_REG0_OFFSET 0x017CU +#define FIOPAD_N55_REG0_OFFSET 0x0180U +#define FIOPAD_C53_REG0_OFFSET 0x0184U +#define FIOPAD_E53_REG0_OFFSET 0x0188U +#define FIOPAD_E27_REG0_OFFSET 0x018CU +#define FIOPAD_G27_REG0_OFFSET 0x0190U +#define FIOPAD_N37_REG0_OFFSET 0x0194U +#define FIOPAD_N35_REG0_OFFSET 0x0198U +#define FIOPAD_J29_REG0_OFFSET 0x019CU +#define FIOPAD_N29_REG0_OFFSET 0x01A0U +#define FIOPAD_L29_REG0_OFFSET 0x01A4U +#define FIOPAD_N41_REG0_OFFSET 0x01A8U +#define FIOPAD_N39_REG0_OFFSET 0x01ACU +#define FIOPAD_L27_REG0_OFFSET 0x01B0U +#define FIOPAD_J27_REG0_OFFSET 0x01B4U +#define FIOPAD_J25_REG0_OFFSET 0x01B8U +#define FIOPAD_E25_REG0_OFFSET 0x01BCU +#define FIOPAD_G25_REG0_OFFSET 0x01C0U +#define FIOPAD_N23_REG0_OFFSET 0x01C4U +#define FIOPAD_L25_REG0_OFFSET 0x01C8U +#define FIOPAD_J33_REG0_OFFSET 0x01CCU +#define FIOPAD_J35_REG0_OFFSET 0x01D0U +#define FIOPAD_G37_REG0_OFFSET 0x01D4U +#define FIOPAD_E39_REG0_OFFSET 0x01D8U +#define FIOPAD_L39_REG0_OFFSET 0x01DCU +#define FIOPAD_C39_REG0_OFFSET 0x01E0U +#define FIOPAD_E37_REG0_OFFSET 0x01E4U +#define FIOPAD_L41_REG0_OFFSET 0x01E8U +#define FIOPAD_J39_REG0_OFFSET 0x01ECU +#define FIOPAD_J37_REG0_OFFSET 0x01F0U +#define FIOPAD_L35_REG0_OFFSET 0x01F4U +#define FIOPAD_E33_REG0_OFFSET 0x01F8U +#define FIOPAD_E31_REG0_OFFSET 0x01FCU +#define FIOPAD_G31_REG0_OFFSET 0x0200U +#define FIOPAD_J31_REG0_OFFSET 0x0204U +#define FIOPAD_L33_REG0_OFFSET 0x0208U +#define FIOPAD_N31_REG0_OFFSET 0x020CU +#define FIOPAD_R47_REG0_OFFSET 0x0210U +#define FIOPAD_R45_REG0_OFFSET 0x0214U +#define FIOPAD_N47_REG0_OFFSET 0x0218U +#define FIOPAD_N51_REG0_OFFSET 0x021CU +#define FIOPAD_L51_REG0_OFFSET 0x0220U +#define FIOPAD_J51_REG0_OFFSET 0x0224U +#define FIOPAD_J41_REG0_OFFSET 0x0228U +#define FIOPAD_E43_REG0_OFFSET 0x022CU +#define FIOPAD_G43_REG0_OFFSET 0x0230U +#define FIOPAD_J43_REG0_OFFSET 0x0234U +#define FIOPAD_J45_REG0_OFFSET 0x0238U +#define FIOPAD_N45_REG0_OFFSET 0x023CU +#define FIOPAD_L47_REG0_OFFSET 0x0240U +#define FIOPAD_L45_REG0_OFFSET 0x0244U +#define FIOPAD_N49_REG0_OFFSET 0x0248U +#define FIOPAD_J49_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ51_REG1_OFFSET 0x1024U +#define FIOPAD_AL51_REG1_OFFSET 0x1028U +#define FIOPAD_AL49_REG1_OFFSET 0x102CU +#define FIOPAD_AN47_REG1_OFFSET 0x1030U +#define FIOPAD_AR47_REG1_OFFSET 0x1034U +#define FIOPAD_AJ53_REG1_OFFSET 0x1058U +#define FIOPAD_AG55_REG1_OFFSET 0x105CU +#define FIOPAD_AG53_REG1_OFFSET 0x1060U +#define FIOPAD_AE55_REG1_OFFSET 0x1064U +#define FIOPAD_BA51_REG1_OFFSET 0x1074U +#define FIOPAD_BA49_REG1_OFFSET 0x1078U +#define FIOPAD_AR55_REG1_OFFSET 0x107CU +#define FIOPAD_AU55_REG1_OFFSET 0x1080U +#define FIOPAD_A41_REG1_OFFSET 0x10D0U +#define FIOPAD_C41_REG1_OFFSET 0x10D4U +#define FIOPAD_A43_REG1_OFFSET 0x10D8U +#define FIOPAD_A45_REG1_OFFSET 0x10DCU +#define FIOPAD_C45_REG1_OFFSET 0x10E0U +#define FIOPAD_A47_REG1_OFFSET 0x10E4U +#define FIOPAD_A29_REG1_OFFSET 0x10E8U +#define FIOPAD_C29_REG1_OFFSET 0x10ECU +#define FIOPAD_C27_REG1_OFFSET 0x10F0U +#define FIOPAD_A27_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U +#define FIOPAD_AL45_REG1_OFFSET 0x10FCU +#define FIOPAD_AL43_REG1_OFFSET 0x1100U +#define FIOPAD_AN45_REG1_OFFSET 0x1104U +#define FIOPAD_AG47_REG1_OFFSET 0x1108U +#define FIOPAD_AJ47_REG1_OFFSET 0x110CU +#define FIOPAD_AG45_REG1_OFFSET 0x1110U +#define FIOPAD_AE51_REG1_OFFSET 0x1114U +#define FIOPAD_AE49_REG1_OFFSET 0x1118U +#define FIOPAD_AG51_REG1_OFFSET 0x111CU +#define FIOPAD_AJ45_REG1_OFFSET 0x1120U +#define FIOPAD_AC51_REG1_OFFSET 0x1124U +#define FIOPAD_AC49_REG1_OFFSET 0x1128U +#define FIOPAD_AE47_REG1_OFFSET 0x112CU +#define FIOPAD_W47_REG1_OFFSET 0x1130U +#define FIOPAD_W49_REG1_OFFSET 0x1138U +#define FIOPAD_U51_REG1_OFFSET 0x113CU +#define FIOPAD_U49_REG1_OFFSET 0x1140U +#define FIOPAD_AE45_REG1_OFFSET 0x1144U +#define FIOPAD_AC45_REG1_OFFSET 0x1148U +#define FIOPAD_AE43_REG1_OFFSET 0x114CU +#define FIOPAD_AA43_REG1_OFFSET 0x1150U +#define FIOPAD_AA45_REG1_OFFSET 0x1154U +#define FIOPAD_W45_REG1_OFFSET 0x1158U +#define FIOPAD_AA47_REG1_OFFSET 0x115CU +#define FIOPAD_U45_REG1_OFFSET 0x1160U +#define FIOPAD_J55_REG1_OFFSET 0x1168U +#define FIOPAD_L53_REG1_OFFSET 0x116CU +#define FIOPAD_C55_REG1_OFFSET 0x1170U +#define FIOPAD_E55_REG1_OFFSET 0x1174U +#define FIOPAD_J53_REG1_OFFSET 0x1178U +#define FIOPAD_L55_REG1_OFFSET 0x117CU +#define FIOPAD_N55_REG1_OFFSET 0x1180U +#define FIOPAD_E27_REG1_OFFSET 0x118CU +#define FIOPAD_G27_REG1_OFFSET 0x1190U +#define FIOPAD_N37_REG1_OFFSET 0x1194U +#define FIOPAD_N35_REG1_OFFSET 0x1198U +#define FIOPAD_J29_REG1_OFFSET 0x119CU +#define FIOPAD_N29_REG1_OFFSET 0x11A0U +#define FIOPAD_L29_REG1_OFFSET 0x11A4U +#define FIOPAD_N41_REG1_OFFSET 0x11A8U +#define FIOPAD_N39_REG1_OFFSET 0x11ACU +#define FIOPAD_L27_REG1_OFFSET 0x11B0U +#define FIOPAD_J27_REG1_OFFSET 0x11B4U +#define FIOPAD_J25_REG1_OFFSET 0x11B8U +#define FIOPAD_E25_REG1_OFFSET 0x11BCU +#define FIOPAD_G25_REG1_OFFSET 0x11C0U +#define FIOPAD_J33_REG1_OFFSET 0x11CCU +#define FIOPAD_J35_REG1_OFFSET 0x11D0U +#define FIOPAD_G37_REG1_OFFSET 0x11D4U +#define FIOPAD_E39_REG1_OFFSET 0x11D8U +#define FIOPAD_L39_REG1_OFFSET 0x11DCU +#define FIOPAD_C39_REG1_OFFSET 0x11E0U +#define FIOPAD_E37_REG1_OFFSET 0x11E4U +#define FIOPAD_L41_REG1_OFFSET 0x11E8U +#define FIOPAD_J39_REG1_OFFSET 0x11ECU +#define FIOPAD_J37_REG1_OFFSET 0x11F0U +#define FIOPAD_L35_REG1_OFFSET 0x11F4U +#define FIOPAD_E33_REG1_OFFSET 0x11F8U +#define FIOPAD_E31_REG1_OFFSET 0x11FCU +#define FIOPAD_G31_REG1_OFFSET 0x1200U +#define FIOPAD_L51_REG1_OFFSET 0x1220U +#define FIOPAD_J51_REG1_OFFSET 0x1224U +#define FIOPAD_J41_REG1_OFFSET 0x1228U +#define FIOPAD_E43_REG1_OFFSET 0x122CU +#define FIOPAD_G43_REG1_OFFSET 0x1230U +#define FIOPAD_J43_REG1_OFFSET 0x1234U +#define FIOPAD_J45_REG1_OFFSET 0x1238U +#define FIOPAD_N45_REG1_OFFSET 0x123CU +#define FIOPAD_L47_REG1_OFFSET 0x1240U +#define FIOPAD_L45_REG1_OFFSET 0x1244U +#define FIOPAD_N49_REG1_OFFSET 0x1248U +#define FIOPAD_J49_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET + + +#define FIOPAD_FUNC0 0x0 +#define FIOPAD_FUNC1 0x1 +#define FIOPAD_FUNC2 0x2 +#define FIOPAD_FUNC3 0x3 +#define FIOPAD_FUNC4 0x4 +#define FIOPAD_FUNC5 0x5 +#define FIOPAD_FUNC6 0x6 +#define FIOPAD_FUNC7 0x7 + +#define PHYTIUM_PINMUX(pin_reg_offset, func_num) (pin_reg_offset) (func_num) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/phytium-pe2204-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/phytium-pe2204-pinctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..9bf9b8a8fd9091bec72f05316fb91a7b24a0c2e0 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/phytium-pe2204-pinctrl.h @@ -0,0 +1,278 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PHYTIUM_PINCTRL_H_ + +#define FIOPAD_AN59_REG0_OFFSET 0x0000U +#define FIOPAD_AW47_REG0_OFFSET 0x0004U +#define FIOPAD_AR55_REG0_OFFSET 0x0020U +#define FIOPAD_AJ55_REG0_OFFSET 0x0024U +#define FIOPAD_AL55_REG0_OFFSET 0x0028U +#define FIOPAD_AL53_REG0_OFFSET 0x002CU +#define FIOPAD_AN51_REG0_OFFSET 0x0030U +#define FIOPAD_AR51_REG0_OFFSET 0x0034U +#define FIOPAD_BA57_REG0_OFFSET 0x0038U +#define FIOPAD_BA59_REG0_OFFSET 0x003CU +#define FIOPAD_AW57_REG0_OFFSET 0x0040U +#define FIOPAD_AW59_REG0_OFFSET 0x0044U +#define FIOPAD_AU55_REG0_OFFSET 0x0048U +#define FIOPAD_AN57_REG0_OFFSET 0x004CU +#define FIOPAD_AL59_REG0_OFFSET 0x0050U +#define FIOPAD_AJ59_REG0_OFFSET 0x0054U +#define FIOPAD_AJ57_REG0_OFFSET 0x0058U +#define FIOPAD_AG59_REG0_OFFSET 0x005CU +#define FIOPAD_AG57_REG0_OFFSET 0x0060U +#define FIOPAD_AE59_REG0_OFFSET 0x0064U +#define FIOPAD_AC59_REG0_OFFSET 0x0068U +#define FIOPAD_AC57_REG0_OFFSET 0x006CU +#define FIOPAD_AR49_REG0_OFFSET 0x0070U +#define FIOPAD_BA55_REG0_OFFSET 0x0074U +#define FIOPAD_BA53_REG0_OFFSET 0x0078U +#define FIOPAD_AR59_REG0_OFFSET 0x007CU +#define FIOPAD_AU59_REG0_OFFSET 0x0080U +#define FIOPAD_AR57_REG0_OFFSET 0x0084U +#define FIOPAD_BA49_REG0_OFFSET 0x0088U +#define FIOPAD_AW55_REG0_OFFSET 0x008CU +#define FIOPAD_A35_REG0_OFFSET 0x0090U +#define FIOPAD_R57_REG0_OFFSET 0x0094U +#define FIOPAD_R59_REG0_OFFSET 0x0098U +#define FIOPAD_U59_REG0_OFFSET 0x009CU +#define FIOPAD_W59_REG0_OFFSET 0x00A0U +#define FIOPAD_U57_REG0_OFFSET 0x00A4U +#define FIOPAD_AA57_REG0_OFFSET 0x00A8U +#define FIOPAD_AA59_REG0_OFFSET 0x00ACU +#define FIOPAD_AW51_REG0_OFFSET 0x00B0U +#define FIOPAD_AU51_REG0_OFFSET 0x00B4U +#define FIOPAD_A39_REG0_OFFSET 0x00B8U +#define FIOPAD_C39_REG0_OFFSET 0x00BCU +#define FIOPAD_C37_REG0_OFFSET 0x00C0U +#define FIOPAD_A37_REG0_OFFSET 0x00C4U +#define FIOPAD_A41_REG0_OFFSET 0x00C8U +#define FIOPAD_A43_REG0_OFFSET 0x00CCU +#define FIOPAD_A45_REG0_OFFSET 0x00D0U +#define FIOPAD_C45_REG0_OFFSET 0x00D4U +#define FIOPAD_A47_REG0_OFFSET 0x00D8U +#define FIOPAD_A49_REG0_OFFSET 0x00DCU +#define FIOPAD_C49_REG0_OFFSET 0x00E0U +#define FIOPAD_A51_REG0_OFFSET 0x00E4U +#define FIOPAD_A33_REG0_OFFSET 0x00E8U +#define FIOPAD_C33_REG0_OFFSET 0x00ECU +#define FIOPAD_C31_REG0_OFFSET 0x00F0U +#define FIOPAD_A31_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ53_REG0_OFFSET 0x00F8U +#define FIOPAD_AL49_REG0_OFFSET 0x00FCU +#define FIOPAD_AL47_REG0_OFFSET 0x0100U +#define FIOPAD_AN49_REG0_OFFSET 0x0104U +#define FIOPAD_AG51_REG0_OFFSET 0x0108U +#define FIOPAD_AJ51_REG0_OFFSET 0x010CU +#define FIOPAD_AG49_REG0_OFFSET 0x0110U +#define FIOPAD_AE55_REG0_OFFSET 0x0114U +#define FIOPAD_AE53_REG0_OFFSET 0x0118U +#define FIOPAD_AG55_REG0_OFFSET 0x011CU +#define FIOPAD_AJ49_REG0_OFFSET 0x0120U +#define FIOPAD_AC55_REG0_OFFSET 0x0124U +#define FIOPAD_AC53_REG0_OFFSET 0x0128U +#define FIOPAD_AE51_REG0_OFFSET 0x012CU +#define FIOPAD_W51_REG0_OFFSET 0x0130U +#define FIOPAD_W55_REG0_OFFSET 0x0134U +#define FIOPAD_W53_REG0_OFFSET 0x0138U +#define FIOPAD_U55_REG0_OFFSET 0x013CU +#define FIOPAD_U53_REG0_OFFSET 0x0140U +#define FIOPAD_AE49_REG0_OFFSET 0x0144U +#define FIOPAD_AC49_REG0_OFFSET 0x0148U +#define FIOPAD_AE47_REG0_OFFSET 0x014CU +#define FIOPAD_AA47_REG0_OFFSET 0x0150U +#define FIOPAD_AA49_REG0_OFFSET 0x0154U +#define FIOPAD_W49_REG0_OFFSET 0x0158U +#define FIOPAD_AA51_REG0_OFFSET 0x015CU +#define FIOPAD_U49_REG0_OFFSET 0x0160U +#define FIOPAD_G59_REG0_OFFSET 0x0164U +#define FIOPAD_J59_REG0_OFFSET 0x0168U +#define FIOPAD_L57_REG0_OFFSET 0x016CU +#define FIOPAD_C59_REG0_OFFSET 0x0170U +#define FIOPAD_E59_REG0_OFFSET 0x0174U +#define FIOPAD_J57_REG0_OFFSET 0x0178U +#define FIOPAD_L59_REG0_OFFSET 0x017CU +#define FIOPAD_N59_REG0_OFFSET 0x0180U +#define FIOPAD_C57_REG0_OFFSET 0x0184U +#define FIOPAD_E57_REG0_OFFSET 0x0188U +#define FIOPAD_E31_REG0_OFFSET 0x018CU +#define FIOPAD_G31_REG0_OFFSET 0x0190U +#define FIOPAD_N41_REG0_OFFSET 0x0194U +#define FIOPAD_N39_REG0_OFFSET 0x0198U +#define FIOPAD_J33_REG0_OFFSET 0x019CU +#define FIOPAD_N33_REG0_OFFSET 0x01A0U +#define FIOPAD_L33_REG0_OFFSET 0x01A4U +#define FIOPAD_N45_REG0_OFFSET 0x01A8U +#define FIOPAD_N43_REG0_OFFSET 0x01ACU +#define FIOPAD_L31_REG0_OFFSET 0x01B0U +#define FIOPAD_J31_REG0_OFFSET 0x01B4U +#define FIOPAD_J29_REG0_OFFSET 0x01B8U +#define FIOPAD_E29_REG0_OFFSET 0x01BCU +#define FIOPAD_G29_REG0_OFFSET 0x01C0U +#define FIOPAD_N27_REG0_OFFSET 0x01C4U +#define FIOPAD_L29_REG0_OFFSET 0x01C8U +#define FIOPAD_J37_REG0_OFFSET 0x01CCU +#define FIOPAD_J39_REG0_OFFSET 0x01D0U +#define FIOPAD_G41_REG0_OFFSET 0x01D4U +#define FIOPAD_E43_REG0_OFFSET 0x01D8U +#define FIOPAD_L43_REG0_OFFSET 0x01DCU +#define FIOPAD_C43_REG0_OFFSET 0x01E0U +#define FIOPAD_E41_REG0_OFFSET 0x01E4U +#define FIOPAD_L45_REG0_OFFSET 0x01E8U +#define FIOPAD_J43_REG0_OFFSET 0x01ECU +#define FIOPAD_J41_REG0_OFFSET 0x01F0U +#define FIOPAD_L39_REG0_OFFSET 0x01F4U +#define FIOPAD_E37_REG0_OFFSET 0x01F8U +#define FIOPAD_E35_REG0_OFFSET 0x01FCU +#define FIOPAD_G35_REG0_OFFSET 0x0200U +#define FIOPAD_J35_REG0_OFFSET 0x0204U +#define FIOPAD_L37_REG0_OFFSET 0x0208U +#define FIOPAD_N35_REG0_OFFSET 0x020CU +#define FIOPAD_R51_REG0_OFFSET 0x0210U +#define FIOPAD_R49_REG0_OFFSET 0x0214U +#define FIOPAD_N51_REG0_OFFSET 0x0218U +#define FIOPAD_N55_REG0_OFFSET 0x021CU +#define FIOPAD_L55_REG0_OFFSET 0x0220U +#define FIOPAD_J55_REG0_OFFSET 0x0224U +#define FIOPAD_J45_REG0_OFFSET 0x0228U +#define FIOPAD_E47_REG0_OFFSET 0x022CU +#define FIOPAD_G47_REG0_OFFSET 0x0230U +#define FIOPAD_J47_REG0_OFFSET 0x0234U +#define FIOPAD_J49_REG0_OFFSET 0x0238U +#define FIOPAD_N49_REG0_OFFSET 0x023CU +#define FIOPAD_L51_REG0_OFFSET 0x0240U +#define FIOPAD_L49_REG0_OFFSET 0x0244U +#define FIOPAD_N53_REG0_OFFSET 0x0248U +#define FIOPAD_J53_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN59_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J53_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ55_REG1_OFFSET 0x1024U +#define FIOPAD_AL55_REG1_OFFSET 0x1028U +#define FIOPAD_AL53_REG1_OFFSET 0x102CU +#define FIOPAD_AN51_REG1_OFFSET 0x1030U +#define FIOPAD_AR51_REG1_OFFSET 0x1034U +#define FIOPAD_AJ57_REG1_OFFSET 0x1058U +#define FIOPAD_AG59_REG1_OFFSET 0x105CU +#define FIOPAD_AG57_REG1_OFFSET 0x1060U +#define FIOPAD_AE59_REG1_OFFSET 0x1064U +#define FIOPAD_BA55_REG1_OFFSET 0x1074U +#define FIOPAD_BA53_REG1_OFFSET 0x1078U +#define FIOPAD_AR59_REG1_OFFSET 0x107CU +#define FIOPAD_AU59_REG1_OFFSET 0x1080U +#define FIOPAD_A45_REG1_OFFSET 0x10D0U +#define FIOPAD_C45_REG1_OFFSET 0x10D4U +#define FIOPAD_A47_REG1_OFFSET 0x10D8U +#define FIOPAD_A49_REG1_OFFSET 0x10DCU +#define FIOPAD_C49_REG1_OFFSET 0x10E0U +#define FIOPAD_A51_REG1_OFFSET 0x10E4U +#define FIOPAD_A33_REG1_OFFSET 0x10E8U +#define FIOPAD_C33_REG1_OFFSET 0x10ECU +#define FIOPAD_C31_REG1_OFFSET 0x10F0U +#define FIOPAD_A31_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ53_REG1_OFFSET 0x10F8U +#define FIOPAD_AL49_REG1_OFFSET 0x10FCU +#define FIOPAD_AL47_REG1_OFFSET 0x1100U +#define FIOPAD_AN49_REG1_OFFSET 0x1104U +#define FIOPAD_AG51_REG1_OFFSET 0x1108U +#define FIOPAD_AJ51_REG1_OFFSET 0x110CU +#define FIOPAD_AG49_REG1_OFFSET 0x1110U +#define FIOPAD_AE55_REG1_OFFSET 0x1114U +#define FIOPAD_AE53_REG1_OFFSET 0x1118U +#define FIOPAD_AG55_REG1_OFFSET 0x111CU +#define FIOPAD_AJ49_REG1_OFFSET 0x1120U +#define FIOPAD_AC55_REG1_OFFSET 0x1124U +#define FIOPAD_AC53_REG1_OFFSET 0x1128U +#define FIOPAD_AE51_REG1_OFFSET 0x112CU +#define FIOPAD_W51_REG1_OFFSET 0x1130U +#define FIOPAD_W53_REG1_OFFSET 0x1138U +#define FIOPAD_U55_REG1_OFFSET 0x113CU +#define FIOPAD_U53_REG1_OFFSET 0x1140U +#define FIOPAD_AE49_REG1_OFFSET 0x1144U +#define FIOPAD_AC49_REG1_OFFSET 0x1148U +#define FIOPAD_AE47_REG1_OFFSET 0x114CU +#define FIOPAD_AA47_REG1_OFFSET 0x1150U +#define FIOPAD_AA49_REG1_OFFSET 0x1154U +#define FIOPAD_W49_REG1_OFFSET 0x1158U +#define FIOPAD_AA51_REG1_OFFSET 0x115CU +#define FIOPAD_U49_REG1_OFFSET 0x1160U +#define FIOPAD_J59_REG1_OFFSET 0x1168U +#define FIOPAD_L57_REG1_OFFSET 0x116CU +#define FIOPAD_C59_REG1_OFFSET 0x1170U +#define FIOPAD_E59_REG1_OFFSET 0x1174U +#define FIOPAD_J57_REG1_OFFSET 0x1178U +#define FIOPAD_L59_REG1_OFFSET 0x117CU +#define FIOPAD_N59_REG1_OFFSET 0x1180U +#define FIOPAD_E31_REG1_OFFSET 0x118CU +#define FIOPAD_G31_REG1_OFFSET 0x1190U +#define FIOPAD_N41_REG1_OFFSET 0x1194U +#define FIOPAD_N39_REG1_OFFSET 0x1198U +#define FIOPAD_J33_REG1_OFFSET 0x119CU +#define FIOPAD_N33_REG1_OFFSET 0x11A0U +#define FIOPAD_L33_REG1_OFFSET 0x11A4U +#define FIOPAD_N45_REG1_OFFSET 0x11A8U +#define FIOPAD_N43_REG1_OFFSET 0x11ACU +#define FIOPAD_L31_REG1_OFFSET 0x11B0U +#define FIOPAD_J31_REG1_OFFSET 0x11B4U +#define FIOPAD_J29_REG1_OFFSET 0x11B8U +#define FIOPAD_E29_REG1_OFFSET 0x11BCU +#define FIOPAD_G29_REG1_OFFSET 0x11C0U +#define FIOPAD_J37_REG1_OFFSET 0x11CCU +#define FIOPAD_J39_REG1_OFFSET 0x11D0U +#define FIOPAD_G41_REG1_OFFSET 0x11D4U +#define FIOPAD_E43_REG1_OFFSET 0x11D8U +#define FIOPAD_L43_REG1_OFFSET 0x11DCU +#define FIOPAD_C43_REG1_OFFSET 0x11E0U +#define FIOPAD_E41_REG1_OFFSET 0x11E4U +#define FIOPAD_L45_REG1_OFFSET 0x11E8U +#define FIOPAD_J43_REG1_OFFSET 0x11ECU +#define FIOPAD_J41_REG1_OFFSET 0x11F0U +#define FIOPAD_L39_REG1_OFFSET 0x11F4U +#define FIOPAD_E37_REG1_OFFSET 0x11F8U +#define FIOPAD_E35_REG1_OFFSET 0x11FCU +#define FIOPAD_G35_REG1_OFFSET 0x1200U +#define FIOPAD_L55_REG1_OFFSET 0x1220U +#define FIOPAD_J55_REG1_OFFSET 0x1224U +#define FIOPAD_J45_REG1_OFFSET 0x1228U +#define FIOPAD_E47_REG1_OFFSET 0x122CU +#define FIOPAD_G47_REG1_OFFSET 0x1230U +#define FIOPAD_J47_REG1_OFFSET 0x1234U +#define FIOPAD_J49_REG1_OFFSET 0x1238U +#define FIOPAD_N49_REG1_OFFSET 0x123CU +#define FIOPAD_L51_REG1_OFFSET 0x1240U +#define FIOPAD_L49_REG1_OFFSET 0x1244U +#define FIOPAD_N53_REG1_OFFSET 0x1248U +#define FIOPAD_J53_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ55_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J53_REG1_OFFSET + + +#define FIOPAD_FUNC0 0x0 +#define FIOPAD_FUNC1 0x1 +#define FIOPAD_FUNC2 0x2 +#define FIOPAD_FUNC3 0x3 +#define FIOPAD_FUNC4 0x4 +#define FIOPAD_FUNC5 0x5 +#define FIOPAD_FUNC6 0x6 +#define FIOPAD_FUNC7 0x7 + +#define PHYTIUM_PINMUX(pin_reg_offset, func_num) (pin_reg_offset) (func_num) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_ */ diff --git a/makefile b/makefile new file mode 100644 index 0000000000000000000000000000000000000000..ee42ce5071a4885b2e1c81d9ca2b17bf2ebd8c49 --- /dev/null +++ b/makefile @@ -0,0 +1,32 @@ + + +boot_smp_el2: +# west build -b e2000d_demo_smp samples/arch/smp/pktqueue +# west build -b e2000d_demo_el2_smp samples/hello_world + west build -b e2000q_demo_el2_smp samples/arch/smp/pi + cp ./build/zephyr/zephyr.elf /mnt/d/tftpboot/baremetal.elf + scp ./build/zephyr/zephyr.elf root@10.31.32.21:/home/zhugy/tftpboot/huanghe/baremetal.elf + +boot: + west build -b e2000q_demo_el2_smp samples/hello_world + cp ./build/zephyr/zephyr.elf /mnt/d/tftpboot/baremetal.elf +# scp ./build/zephyr/zephyr.elf root@10.31.32.21:/home/zhugy/tftpboot/huanghe/baremetal.elf + +menuconfig: + west build -t menuconfig + +boot_gdb: + west build -b qemu_cortex_a53_smp samples/hello_world + +clean: + west build -t clean + +debug_qemu: + west build -t debugserver_qemu + +gdb: + gdb-multiarch -x .gdbinit + + +gdb_qemu: + gdb-multiarch -x .gitlint_qemu diff --git a/modules/Kconfig b/modules/Kconfig index 9d5abd1f4b049e789b5eac588da73d9bcb0b35c4..16d15779e724171379ac2c0d175bb346aee7accb 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -44,6 +44,7 @@ source "modules/zcbor/Kconfig" source "modules/Kconfig.mcuboot" source "modules/Kconfig.intel" source "modules/hostap/Kconfig" +source "modules/Kconfig.phytium" comment "Unavailable modules, please install those via the project manifest." diff --git a/modules/Kconfig.phytium b/modules/Kconfig.phytium new file mode 100644 index 0000000000000000000000000000000000000000..41bae1d0a1ab8240ed8f9be6393abb8d1c6f7d8d --- /dev/null +++ b/modules/Kconfig.phytium @@ -0,0 +1,52 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config PHYTIUM_SOFT + bool + +config PHYTIUM_STANDALONE_SDK + bool + depends on PHYTIUM_SOFT + +if PHYTIUM_STANDALONE_SDK + +config USE_SERIAL + bool + prompt "Use serial" + default y + help + Include serial modules and enable serial + +if USE_SERIAL + config ENABLE_Pl011_UART + bool + prompt "Use Pl011 uart" + default y +endif + +config USE_SDHC + bool + prompt "Use SDHC" + default y + +if USE_SDHC + config ENABLE_PHYTIUM_SDHC + bool + prompt "Use phytium sdhc" + default nn + +endif + +endif \ No newline at end of file diff --git a/samples/arch/smp/pktqueue/src/main.c b/samples/arch/smp/pktqueue/src/main.c index cfffd813a8bc2b8d2a0e4a94203df3511a2c390f..fd57e1de0796ccadda3a4d7eaff01e9f67f8a73a 100644 --- a/samples/arch/smp/pktqueue/src/main.c +++ b/samples/arch/smp/pktqueue/src/main.c @@ -25,7 +25,7 @@ #define CRC_BYTE_1 10 #define CRC_BYTE_2 11 -#define STACK_SIZE 2048 +#define STACK_SIZE 4096 static struct k_thread tthread[THREADS_NUM*QUEUE_NUM]; static struct k_thread qthread[QUEUE_NUM]; diff --git a/samples/userspace/hello_world_user/prj.conf b/samples/userspace/hello_world_user/prj.conf index 7de714c1418ed15f8e2e4334f7d9466ea4d83e59..c4bfc740a08bbefb4830d426fe55be9a81958efc 100644 --- a/samples/userspace/hello_world_user/prj.conf +++ b/samples/userspace/hello_world_user/prj.conf @@ -1,2 +1,4 @@ + + CONFIG_USERSPACE=y CONFIG_ASSERT=y diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml index c0b2456501e0cdea83db4fbf71301a7cd867de5a..b85073bab34257f053b8255235b7bfbd8250bb86 100644 --- a/soc/arm/soc.yml +++ b/soc/arm/soc.yml @@ -19,6 +19,7 @@ family: socs: - name: designstart_fpga_cortex_m1 - name: designstart_fpga_cortex_m3 + - name: arm64 series: - name: fvp_aemv8a diff --git a/soc/phytium/pd2008/CMakeLists.txt b/soc/phytium/pd2008/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/pd2008/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pd2008/Kconfig b/soc/phytium/pd2008/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..9a244a5b22f4c89674594e1afef725743fabc2ff --- /dev/null +++ b/soc/phytium/pd2008/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PD2008 + select ARM64 + select CPU_PHYTIUM_FTC663 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT diff --git a/soc/phytium/pd2008/Kconfig.defconfig b/soc/phytium/pd2008/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..86b46f460532633346338577d23c5e8a9a07188c --- /dev/null +++ b/soc/phytium/pd2008/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PD2008 + +config SOC + default "pd2008" + +config NUM_IRQS + int + default 159 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 48000000 + +endif diff --git a/soc/phytium/pd2008/Kconfig.soc b/soc/phytium/pd2008/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..d44029a5f8a6bf510f49f147181a28a3c7533a36 --- /dev/null +++ b/soc/phytium/pd2008/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PD2008 + bool "pd2008" + select SOC_FAMILY_ARM64 + +if SOC_PD2008 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pd2008/mmu_regions.c b/soc/phytium/pd2008/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..5f2a0000ad8a916b452bffe0c3425891b7951862 --- /dev/null +++ b/soc/phytium/pd2008/mmu_regions.c @@ -0,0 +1,38 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/pd2008/soc.c b/soc/phytium/pd2008/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..d879c4fb8d102ae9f4dbaf94e6605fd4e40fd4b0 --- /dev/null +++ b/soc/phytium/pd2008/soc.c @@ -0,0 +1,23 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} \ No newline at end of file diff --git a/soc/phytium/pd2008/soc.yml b/soc/phytium/pd2008/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..c4ac9ad36b96c056ca3fe987b565bf2412fb8223 --- /dev/null +++ b/soc/phytium/pd2008/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: pd2008 diff --git a/soc/phytium/pd2008_aarch32/CMakeLists.txt b/soc/phytium/pd2008_aarch32/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..3abcd5f07af72cdcddca86d9503e5a8249c0fa94 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pd2008_aarch32/Kconfig b/soc/phytium/pd2008_aarch32/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5d592cfa59bc6470daee8f05439b8fed4ca8e8a7 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/Kconfig @@ -0,0 +1,32 @@ + +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PD2008_AARCH32 + bool "Phytium pd2008 Soc series" + select SOC_FAMILY_PHYTIUM_PD2008 + select ARM + select CPU_PHYTIUM_FT663 + select PLATFORM_SPECIFIC_INIT + select GIC_SINGLE_SECURITY_STATE + select CACHE_MANAGEMENT + select AARCH64_2_AARCH32 + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT + #select CPU_HAS_FPU + select VFP_DP_D16 + help + Enable support for the Phytium pd2008 + SoC series (8-core Armv8 cpu). \ No newline at end of file diff --git a/soc/phytium/pd2008_aarch32/Kconfig.defconfig b/soc/phytium/pd2008_aarch32/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..66e6abf7671556dbacc4fc5fa5859098a87ce179 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PD2008_AARCH32 + +config SOC + default "pd2008_aarch32" + +config NUM_IRQS + int + default 159 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 48000000 + +endif diff --git a/soc/phytium/pd2008_aarch32/Kconfig.soc b/soc/phytium/pd2008_aarch32/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..e9d5cd6169e96be7297d9a79a77bcbedc14d0fb2 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PD2008_AARCH32 + bool "pd2008_aarch32" + select SOC_FAMILY_ARM + +if SOC_PD2008_AARCH32 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pd2008_aarch32/soc.c b/soc/phytium/pd2008_aarch32/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..bbb92f33a94b91093dc30d44144127b9f5cf238e --- /dev/null +++ b/soc/phytium/pd2008_aarch32/soc.c @@ -0,0 +1,57 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include +extern void *_vector_table[]; + + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + +void z_arm_platform_init(void) +{ + /* + * Use normal exception vectors address range (0x0-0x1C). + */ + unsigned int sctlr; + + __set_VBAR((uintptr_t)_vector_table); + + sctlr = 0; + __set_SCTLR(sctlr); +} + +void relocate_vector_table(void) +{ + +} \ No newline at end of file diff --git a/soc/phytium/pd2008_aarch32/soc.h b/soc/phytium/pd2008_aarch32/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..23e4823671e82cb4bb47ccef8db16cd4e9982589 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/soc.h @@ -0,0 +1,22 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef _BOARD__H_ +#define _BOARD__H_ + +/* Define CMSIS configurations */ +#define __GIC_PRESENT 0 +#define __TIM_PRESENT 0 +#endif /* _BOARD__H_ */ \ No newline at end of file diff --git a/soc/phytium/pd2008_aarch32/soc.yml b/soc/phytium/pd2008_aarch32/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..cc0dfc8d48d9cde0dd94e288f799c793c0d30491 --- /dev/null +++ b/soc/phytium/pd2008_aarch32/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm + socs: + - name: pd2008_aarch32 diff --git a/soc/phytium/pd2308/CMakeLists.txt b/soc/phytium/pd2308/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/pd2308/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pd2308/Kconfig b/soc/phytium/pd2308/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..708224fbd0b43a2e6e85685805cca04dc02235fe --- /dev/null +++ b/soc/phytium/pd2308/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PD2308 + select ARM64 + select CPU_PHYTIUM_FTC862 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT diff --git a/soc/phytium/pd2308/Kconfig.defconfig b/soc/phytium/pd2308/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..06e1237c322805add0c3b4c9fe75b9e2a3337651 --- /dev/null +++ b/soc/phytium/pd2308/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PD2308 + +config SOC + default "pd2308" + +config NUM_IRQS + int + default 195 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pd2308/Kconfig.soc b/soc/phytium/pd2308/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..50c230a230957875a198062317c9606afb3cfc0a --- /dev/null +++ b/soc/phytium/pd2308/Kconfig.soc @@ -0,0 +1,27 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PD2308 + bool "pd2308" + select SOC_FAMILY_ARM64 + +config SOC + default "soc_pd2308" if SOC_PD2308 + +if SOC_PD2308 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif diff --git a/soc/phytium/pd2308/mmu_regions.c b/soc/phytium/pd2308/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..6c51737df3f100d06ab44ac572e846b81592dca3 --- /dev/null +++ b/soc/phytium/pd2308/mmu_regions.c @@ -0,0 +1,52 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: mmu_regions.c + * Created Date: 2024-10-11 14:03:59 + * Last Modified: 2024-10-15 13:43:05 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("UART1", + DT_REG_ADDR(DT_INST(0, arm_pl011)), + DT_REG_SIZE(DT_INST(0, arm_pl011)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/pd2308/pinctrl_soc.h b/soc/phytium/pd2308/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..40628b5fce66643508685ffaec873bafab44da8a --- /dev/null +++ b/soc/phytium/pd2308/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PD2308_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PD2308_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PD2308_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PD2308_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pd2308/soc.c b/soc/phytium/pd2308/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..71dc4ec670dd89c8a40e1772d82c7445574a76b2 --- /dev/null +++ b/soc/phytium/pd2308/soc.c @@ -0,0 +1,32 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: soc.c + * Created Date: 2024-12-04 16:39:00 + * Last Modified: 2024-12-04 16:39:01 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} diff --git a/soc/phytium/pd2308/soc.yml b/soc/phytium/pd2308/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..e638d2389c4682e6c38dd02e16ac210f4c4ca7a9 --- /dev/null +++ b/soc/phytium/pd2308/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: pd2308 diff --git a/soc/phytium/pd2408/CMakeLists.txt b/soc/phytium/pd2408/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/pd2408/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pd2408/Kconfig b/soc/phytium/pd2408/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..ef7ec4d7bff1cc230f14c76d48219afedc837428 --- /dev/null +++ b/soc/phytium/pd2408/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PD2408 + select ARM64 + select CPU_PHYTIUM_FTC862 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT diff --git a/soc/phytium/pd2408/Kconfig.defconfig b/soc/phytium/pd2408/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..e197a49b94a6821dcee5e90f4df47126694b7d33 --- /dev/null +++ b/soc/phytium/pd2408/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PD2408 + +config SOC + default "pd2408" + +config NUM_IRQS + int + default 195 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pd2408/Kconfig.soc b/soc/phytium/pd2408/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..49f16e8ac934e2e20542ead759f84e92d23f8fd5 --- /dev/null +++ b/soc/phytium/pd2408/Kconfig.soc @@ -0,0 +1,27 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PD2408 + bool "pd2408" + select SOC_FAMILY_ARM64 + +config SOC + default "soc_pd2408" if SOC_PD2408 + +if SOC_PD2408 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif diff --git a/soc/phytium/pd2408/mmu_regions.c b/soc/phytium/pd2408/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..6c51737df3f100d06ab44ac572e846b81592dca3 --- /dev/null +++ b/soc/phytium/pd2408/mmu_regions.c @@ -0,0 +1,52 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: mmu_regions.c + * Created Date: 2024-10-11 14:03:59 + * Last Modified: 2024-10-15 13:43:05 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("UART1", + DT_REG_ADDR(DT_INST(0, arm_pl011)), + DT_REG_SIZE(DT_INST(0, arm_pl011)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/pd2408/pinctrl_soc.h b/soc/phytium/pd2408/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..33b74d57db6bf0a06e5a309b2663e19005dbfd34 --- /dev/null +++ b/soc/phytium/pd2408/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PD2408_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PD2408_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PD2408_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PD2408_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pd2408/soc.c b/soc/phytium/pd2408/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..71dc4ec670dd89c8a40e1772d82c7445574a76b2 --- /dev/null +++ b/soc/phytium/pd2408/soc.c @@ -0,0 +1,32 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: soc.c + * Created Date: 2024-12-04 16:39:00 + * Last Modified: 2024-12-04 16:39:01 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} diff --git a/soc/phytium/pd2408/soc.yml b/soc/phytium/pd2408/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..3cee8395b7affa80288ea8d40c6b9363a31e9d1b --- /dev/null +++ b/soc/phytium/pd2408/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: pd2408 diff --git a/soc/phytium/pe2202/CMakeLists.txt b/soc/phytium/pe2202/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/pe2202/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pe2202/Kconfig b/soc/phytium/pe2202/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2dc4c7895f35e884e77869a193f90b1a30bf9a17 --- /dev/null +++ b/soc/phytium/pe2202/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PE2202 + select ARM64 + select CPU_PHYTIUM_FTC310 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT \ No newline at end of file diff --git a/soc/phytium/pe2202/Kconfig.defconfig b/soc/phytium/pe2202/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..17253e6f8f9be0c43ced7be7be650ceecc12311c --- /dev/null +++ b/soc/phytium/pe2202/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PE2202 + +config SOC + default "pe2202" + +config NUM_IRQS + int + default 266 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pe2202/Kconfig.soc b/soc/phytium/pe2202/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..6bd7d84044bffc513acbcd3dad9a19593eedb5e9 --- /dev/null +++ b/soc/phytium/pe2202/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2202 + bool "pe2202" + select SOC_FAMILY_ARM64 + +if SOC_PE2202 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pe2202/mmu_regions.c b/soc/phytium/pe2202/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..5f2a0000ad8a916b452bffe0c3425891b7951862 --- /dev/null +++ b/soc/phytium/pe2202/mmu_regions.c @@ -0,0 +1,38 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/pe2202/pinctrl_soc.h b/soc/phytium/pe2202/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..99c9648dcd941c66759bff2ae4006635f4cd40ed --- /dev/null +++ b/soc/phytium/pe2202/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PE2202_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PE2202_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PE2202_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PE2202_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pe2202/soc.c b/soc/phytium/pe2202/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..9b67afdc7b700323624b5b3c62bf45b576860c45 --- /dev/null +++ b/soc/phytium/pe2202/soc.c @@ -0,0 +1,23 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} diff --git a/soc/phytium/pe2202/soc.h b/soc/phytium/pe2202/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/soc/phytium/pe2202/soc.yml b/soc/phytium/pe2202/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..e519b35292f63c8fa3d198be3b4c9e3572ddcf97 --- /dev/null +++ b/soc/phytium/pe2202/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: pe2202 diff --git a/soc/phytium/pe2202_aarch32/CMakeLists.txt b/soc/phytium/pe2202_aarch32/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..3abcd5f07af72cdcddca86d9503e5a8249c0fa94 --- /dev/null +++ b/soc/phytium/pe2202_aarch32/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pe2202_aarch32/Kconfig b/soc/phytium/pe2202_aarch32/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7536aada3874104dc1830f1c2b5dff71e056c88c --- /dev/null +++ b/soc/phytium/pe2202_aarch32/Kconfig @@ -0,0 +1,31 @@ + +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2202_AARCH32 + bool "Phytium E2000 Soc series" + select ARM + select CPU_PHYTIUM_FT310 + select PLATFORM_SPECIFIC_INIT + select GIC_SINGLE_SECURITY_STATE + select CACHE_MANAGEMENT + select AARCH64_2_AARCH32 + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT + #select CPU_HAS_FPU + select VFP_DP_D16 + help + Enable support for the Phytium pe2202 + SoC series (4-core Armv8 cpu). \ No newline at end of file diff --git a/soc/phytium/pe2202_aarch32/Kconfig.defconfig b/soc/phytium/pe2202_aarch32/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..62ad79852655c7967a6e15382732a83f3e19e37f --- /dev/null +++ b/soc/phytium/pe2202_aarch32/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PE2202_AARCH32 + +config SOC + default "pe2202_aarch32" + +config NUM_IRQS + int + default 266 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pe2202_aarch32/Kconfig.soc b/soc/phytium/pe2202_aarch32/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..15940a0aaa48f0b23527ff557ee1f6fdee7852fe --- /dev/null +++ b/soc/phytium/pe2202_aarch32/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2202_AARCH32 + bool "pe2202_aarch32" + select SOC_FAMILY_ARM + +if SOC_PE2202_AARCH32 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pe2202_aarch32/pinctrl_soc.h b/soc/phytium/pe2202_aarch32/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..92ae93572a6affa0b031ce0059c3be9336cf6db5 --- /dev/null +++ b/soc/phytium/pe2202_aarch32/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PE2204_AARCH32_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PE2204_AARCH32_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PE2204_AARCH32_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PE2204_AARCH32_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pe2202_aarch32/soc.c b/soc/phytium/pe2202_aarch32/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..bbb92f33a94b91093dc30d44144127b9f5cf238e --- /dev/null +++ b/soc/phytium/pe2202_aarch32/soc.c @@ -0,0 +1,57 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include +extern void *_vector_table[]; + + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + +void z_arm_platform_init(void) +{ + /* + * Use normal exception vectors address range (0x0-0x1C). + */ + unsigned int sctlr; + + __set_VBAR((uintptr_t)_vector_table); + + sctlr = 0; + __set_SCTLR(sctlr); +} + +void relocate_vector_table(void) +{ + +} \ No newline at end of file diff --git a/soc/phytium/pe2202_aarch32/soc.h b/soc/phytium/pe2202_aarch32/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..23e4823671e82cb4bb47ccef8db16cd4e9982589 --- /dev/null +++ b/soc/phytium/pe2202_aarch32/soc.h @@ -0,0 +1,22 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef _BOARD__H_ +#define _BOARD__H_ + +/* Define CMSIS configurations */ +#define __GIC_PRESENT 0 +#define __TIM_PRESENT 0 +#endif /* _BOARD__H_ */ \ No newline at end of file diff --git a/soc/phytium/pe2202_aarch32/soc.yml b/soc/phytium/pe2202_aarch32/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..b6ce5651e2d6f24f249077d86dc62b170c17bedc --- /dev/null +++ b/soc/phytium/pe2202_aarch32/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm + socs: + - name: pe2202_aarch32 diff --git a/soc/phytium/pe2204/CMakeLists.txt b/soc/phytium/pe2204/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/pe2204/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pe2204/Kconfig b/soc/phytium/pe2204/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..4befee3a9648ebe01788bb4d29c7ec2373598b87 --- /dev/null +++ b/soc/phytium/pe2204/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PE2204 + select ARM64 + select CPU_PHYTIUM_FTC310 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT \ No newline at end of file diff --git a/soc/phytium/pe2204/Kconfig.defconfig b/soc/phytium/pe2204/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..4a99515ed1ce4998f31e1c87b9760fa0446b755a --- /dev/null +++ b/soc/phytium/pe2204/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PE2204 + +config SOC + default "pe2204" + +config NUM_IRQS + int + default 266 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pe2204/Kconfig.soc b/soc/phytium/pe2204/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..d81c3064a16ebc36ec7845b8566926fae084e9e3 --- /dev/null +++ b/soc/phytium/pe2204/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2204 + bool "pe2204" + select SOC_FAMILY_ARM64 + +if SOC_PE2204 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pe2204/mmu_regions.c b/soc/phytium/pe2204/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..5f2a0000ad8a916b452bffe0c3425891b7951862 --- /dev/null +++ b/soc/phytium/pe2204/mmu_regions.c @@ -0,0 +1,38 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/pe2204/pinctrl_soc.h b/soc/phytium/pe2204/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..1436e64b56714086b511b498984e76d03cac68a4 --- /dev/null +++ b/soc/phytium/pe2204/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PE2204_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PE2204_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PE2204_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PE2204_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pe2204/soc.c b/soc/phytium/pe2204/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..d879c4fb8d102ae9f4dbaf94e6605fd4e40fd4b0 --- /dev/null +++ b/soc/phytium/pe2204/soc.c @@ -0,0 +1,23 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} \ No newline at end of file diff --git a/soc/phytium/pe2204/soc.yml b/soc/phytium/pe2204/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..7a41f116ab7f643918d5ebb1938a9aeaa344d903 --- /dev/null +++ b/soc/phytium/pe2204/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: pe2204 diff --git a/soc/phytium/pe2204_aarch32/CMakeLists.txt b/soc/phytium/pe2204_aarch32/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..3abcd5f07af72cdcddca86d9503e5a8249c0fa94 --- /dev/null +++ b/soc/phytium/pe2204_aarch32/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/pe2204_aarch32/Kconfig b/soc/phytium/pe2204_aarch32/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..adce6e9eda0394406e54c73f2ec933bb949d8d49 --- /dev/null +++ b/soc/phytium/pe2204_aarch32/Kconfig @@ -0,0 +1,31 @@ + +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +# +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at +# +# https://opensource.org/license/apache-2-0 +# +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2204_AARCH32 + bool "Phytium PE2004 Soc series" + select ARM + select CPU_PHYTIUM_FT310 + select PLATFORM_SPECIFIC_INIT + select GIC_SINGLE_SECURITY_STATE + select CACHE_MANAGEMENT + select AARCH64_2_AARCH32 + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT + #select CPU_HAS_FPU + select VFP_DP_D16 + help + Enable support for the Phytium pe2204 + SoC series (4-core Armv8 cpu). \ No newline at end of file diff --git a/soc/phytium/pe2204_aarch32/Kconfig.defconfig b/soc/phytium/pe2204_aarch32/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..5f0a46a5bd7f800aebabeef6e275e6fec02c8780 --- /dev/null +++ b/soc/phytium/pe2204_aarch32/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PE2204_AARCH32 + +config SOC + default "pe2204_aarch32" + +config NUM_IRQS + int + default 266 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/pe2204_aarch32/Kconfig.soc b/soc/phytium/pe2204_aarch32/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..eb9f9799f14b1952005cbc24d23681119bef76ce --- /dev/null +++ b/soc/phytium/pe2204_aarch32/Kconfig.soc @@ -0,0 +1,24 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PE2204_AARCH32 + bool "pe2204_aarch32" + select SOC_FAMILY_ARM + +if SOC_PE2204_AARCH32 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif \ No newline at end of file diff --git a/soc/phytium/pe2204_aarch32/pinctrl_soc.h b/soc/phytium/pe2204_aarch32/pinctrl_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..5b57b078ca8b3967242f1bc6a89ba8f9e7d8d260 --- /dev/null +++ b/soc/phytium/pe2204_aarch32/pinctrl_soc.h @@ -0,0 +1,51 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef ZEPHYR_SOC_ARM64_PHYTIUM_PE2202_AARCH32_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_PHYTIUM_PE2202_AARCH32_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pin { + + uint32_t pin_reg_offset; + uint32_t func_num; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define PHYTIUM_PE2202_AARCH32_DT_PIN(node_id) \ + { \ + .pin_reg_offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .func_num = DT_PROP_BY_IDX(node_id, pinmux, 1) \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + PHYTIUM_PE2202_AARCH32_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/soc/phytium/pe2204_aarch32/soc.c b/soc/phytium/pe2204_aarch32/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..bbb92f33a94b91093dc30d44144127b9f5cf238e --- /dev/null +++ b/soc/phytium/pe2204_aarch32/soc.c @@ -0,0 +1,57 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include +#include +#include +extern void *_vector_table[]; + + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + +void z_arm_platform_init(void) +{ + /* + * Use normal exception vectors address range (0x0-0x1C). + */ + unsigned int sctlr; + + __set_VBAR((uintptr_t)_vector_table); + + sctlr = 0; + __set_SCTLR(sctlr); +} + +void relocate_vector_table(void) +{ + +} \ No newline at end of file diff --git a/soc/phytium/pe2204_aarch32/soc.h b/soc/phytium/pe2204_aarch32/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..23e4823671e82cb4bb47ccef8db16cd4e9982589 --- /dev/null +++ b/soc/phytium/pe2204_aarch32/soc.h @@ -0,0 +1,22 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. +// +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at +// +// https://opensource.org/license/apache-2-0 +// +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#ifndef _BOARD__H_ +#define _BOARD__H_ + +/* Define CMSIS configurations */ +#define __GIC_PRESENT 0 +#define __TIM_PRESENT 0 +#endif /* _BOARD__H_ */ \ No newline at end of file diff --git a/soc/phytium/pe2204_aarch32/soc.yml b/soc/phytium/pe2204_aarch32/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..44a923f0319956006894e1409428c62b2244d39b --- /dev/null +++ b/soc/phytium/pe2204_aarch32/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm + socs: + - name: pe2204_aarch32 diff --git a/soc/phytium/ps2316/CMakeLists.txt b/soc/phytium/ps2316/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..801a8ef8fc7194ea4020a8efca4465ae6c9a286b --- /dev/null +++ b/soc/phytium/ps2316/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/phytium/ps2316/Kconfig b/soc/phytium/ps2316/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..22e4c65fd5aade0fa5cfc3f07db4d3a7edffaa48 --- /dev/null +++ b/soc/phytium/ps2316/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 zhangyan +# SPDX-License-Identifier: Apache-2.0 + +config SOC_PS2316 + select ARM64 + select CPU_PHYTIUM_FTC862 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select PHYTIUM_STANDALONE_SDK + select PHYTIUM_SOFT diff --git a/soc/phytium/ps2316/Kconfig.defconfig b/soc/phytium/ps2316/Kconfig.defconfig new file mode 100644 index 0000000000000000000000000000000000000000..da16dd0ceb66f86762fc5ed692f392ddf713ba30 --- /dev/null +++ b/soc/phytium/ps2316/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +if SOC_PS2316 + +config SOC + default "ps2316" + +config NUM_IRQS + int + default 195 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +endif diff --git a/soc/phytium/ps2316/Kconfig.soc b/soc/phytium/ps2316/Kconfig.soc new file mode 100644 index 0000000000000000000000000000000000000000..3771a56f8a96f33242462a84750b6bb75886b53f --- /dev/null +++ b/soc/phytium/ps2316/Kconfig.soc @@ -0,0 +1,27 @@ +# Phytium is pleased to support the open source community by making Zephyr-SDK available. + +# +# Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +# Licensed under the Apache-2.0 License (the "License"); you may not use this file except +# in compliance with the License. You may obtain a copy of the License at + +# https://opensource.org/license/apache-2-0 + +# Unless required by applicable law or agreed to in writing, software distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. + +config SOC_PS2316 + bool "ps2316" + select SOC_FAMILY_ARM64 + +config SOC + default "soc_ps2316" if SOC_PS2316 + +if SOC_PS2316 +config HAL_STANDALONE_SDK_DEBUG + bool "standalone_sdk_debug" + +endif diff --git a/soc/phytium/ps2316/mmu_regions.c b/soc/phytium/ps2316/mmu_regions.c new file mode 100644 index 0000000000000000000000000000000000000000..6c51737df3f100d06ab44ac572e846b81592dca3 --- /dev/null +++ b/soc/phytium/ps2316/mmu_regions.c @@ -0,0 +1,52 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: mmu_regions.c + * Created Date: 2024-10-11 14:03:59 + * Last Modified: 2024-10-15 13:43:05 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("UART1", + DT_REG_ADDR(DT_INST(0, arm_pl011)), + DT_REG_SIZE(DT_INST(0, arm_pl011)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + + + diff --git a/soc/phytium/ps2316/soc.c b/soc/phytium/ps2316/soc.c new file mode 100644 index 0000000000000000000000000000000000000000..d879c4fb8d102ae9f4dbaf94e6605fd4e40fd4b0 --- /dev/null +++ b/soc/phytium/ps2316/soc.c @@ -0,0 +1,23 @@ +// Phytium is pleased to support the open source community by making Zephyr-SDK available. + +// +// Copyright (C) 2024 Phytium Technology Co., Ltd. All rights reserved. + +// Licensed under the Apache-2.0 License (the "License"); you may not use this file except +// in compliance with the License. You may obtain a copy of the License at + +// https://opensource.org/license/apache-2-0 + +// Unless required by applicable law or agreed to in writing, software distributed +// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +#include + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int arch_printk_char_out(int c) +{ + putchar(c) ; + return 0; +} \ No newline at end of file diff --git a/soc/phytium/ps2316/soc.yml b/soc/phytium/ps2316/soc.yml new file mode 100644 index 0000000000000000000000000000000000000000..5a34dcab1f76a4a3e339559f41d5fed5392a64b7 --- /dev/null +++ b/soc/phytium/ps2316/soc.yml @@ -0,0 +1,5 @@ +family: + +- name: arm64 + socs: + - name: ps2316 diff --git a/subsys/sd/sd.c b/subsys/sd/sd.c index f075203601d620f34748cebb95f7373801c96a24..53d87d469395ca372028dd7c72c868aebcc12527 100644 --- a/subsys/sd/sd.c +++ b/subsys/sd/sd.c @@ -209,6 +209,7 @@ static int sd_command_init(struct sd_card *card) } #endif /* CONFIG_SDIO_STACK */ #ifdef CONFIG_SDMMC_STACK + LOG_DBG("sdmmc_card_init is start"); /* Attempt to initialize SDMMC card */ if (!sdmmc_card_init(card)) { return 0; @@ -261,7 +262,7 @@ int sd_init(const struct device *sdhc_dev, struct sd_card *card) k_mutex_unlock(&card->lock); return ret; } - + LOG_DBG("start sd_command_init"); /* * SD protocol is stateful, so we must account for the possibility * that the card is in a bad state. The return code SD_RESTART diff --git a/west.yml b/west.yml index b9a45385d6090fa8156bcce15e1f11f27a7a9823..2b98ca2ae87e6268d27323ab511a27ee0c836dc0 100644 --- a/west.yml +++ b/west.yml @@ -23,325 +23,37 @@ manifest: url-base: https://github.com/zephyrproject-rtos - name: babblesim url-base: https://github.com/BabbleSim + - name: phytium + url-base: https://gitee.com/phytium_embedded group-filter: [-babblesim, -optional] # # Please add items below based on alphabetical order projects: - - name: acpica - revision: 8d24867bc9c9d81c81eeac59391cda59333affd4 - path: modules/lib/acpica - - name: bsim - repo-path: babblesim-manifest - revision: 9351ae1ad44864a49c351f9704f65f43046abeb0 - path: tools/bsim - groups: - - babblesim - - name: babblesim_base - remote: babblesim - repo-path: base - path: tools/bsim/components - revision: 4bd907be0b2abec3b31a23fd8ca98db2a07209d2 - groups: - - babblesim - - name: babblesim_ext_2G4_libPhyComv1 - remote: babblesim - repo-path: ext_2G4_libPhyComv1 - path: tools/bsim/components/ext_2G4_libPhyComv1 - revision: 93f5eba512c438b0c9ebc1b1a947517c865b3643 - groups: - - babblesim - - name: babblesim_ext_2G4_phy_v1 - remote: babblesim - repo-path: ext_2G4_phy_v1 - path: tools/bsim/components/ext_2G4_phy_v1 - revision: 04eeb3c3794444122fbeeb3715f4233b0b50cfbb - groups: - - babblesim - - name: babblesim_ext_2G4_channel_NtNcable - remote: babblesim - repo-path: ext_2G4_channel_NtNcable - path: tools/bsim/components/ext_2G4_channel_NtNcable - revision: 20a38c997f507b0aa53817aab3d73a462fff7af1 - groups: - - babblesim - - name: babblesim_ext_2G4_channel_multiatt - remote: babblesim - repo-path: ext_2G4_channel_multiatt - path: tools/bsim/components/ext_2G4_channel_multiatt - revision: bde72a57384dde7a4310bcf3843469401be93074 - groups: - - babblesim - - name: babblesim_ext_2G4_modem_magic - remote: babblesim - repo-path: ext_2G4_modem_magic - path: tools/bsim/components/ext_2G4_modem_magic - revision: edfcda2d3937a74be0a59d6cd47e0f50183453da - groups: - - babblesim - - name: babblesim_ext_2G4_modem_BLE_simple - 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