# ee260_lab

**Repository Path**: wolver/ee260_lab

## Basic Information

- **Project Name**: ee260_lab
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-07-05
- **Last Updated**: 2026-07-05

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# ee260 - Advanced VLSI Design

## Do it yourself (DIY) Lab for IC Design Resources

Every discussion/Q&A will be at https://github.com/tkimva/ee260_lab. Please use GITHUB page instead of email to ask any question to TA.

### Chapter

| # | Title | Remark | 
| ---- | ---- | -------|
| 1	|	[Pre-Lab - ENGR account checkup / Linux System Basic](lab0)	| | 
| 2	| [Lab/Tutorial 1 - Synopsys Schematic Design (Galaxy Custom Designer)/ Pre-Simulation (HSPICE)](lab1)	| |
| 3	| [Lab/Tutorial 2 - Synopsys Layout Design (Galaxy Custom Designer) / Design Rule Check (DRC) / Verification (LVS)](lab2)  |  | 
| 4		| [Lab/Tutorial 3 - Post-Simulation with Parasitic Extraction (HSPICE). Simple Hierarchical IC Design (Target Circuit: Ring Oscillator)](lab3) | | 
| 5		| [Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 1-bit full adder-no hierarchical design)](lab3)	| | 
| 6	  | [Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 4-bit full adder-use Hierarchical)](lab3) | 	|  
| 7		| [Lab/Tutorial 4 - RTL Synthesis Design (Design Compiler/IC Compiler/PrimeTime) (Target Circuit: 4-bit full adder)](lab4)|| 
| 8		| [Lab/Tutorial 4 - Complex RTL Synthesis Design  (Target Circuit: Euclid's Algorithm for GCD)](lab4)| 	|  
| 9	| [Lab/Tutorial 4 - Full Chip RTL Synthesis Design	(Target Circuit: Core Design)](lab4)|  |